Prasenjit Biswas - researchr alias

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Viewing Publication 1 - 26 from 26

2020

A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model CheckingPrasenjit Biswas, Sarit Pal, Sunil Khatri. icict2 2020: 114-123 [doi]

2017

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value AlgebraPrasenjit Biswas, D. M. H. Walker. vlsid 2017: 141-146 [doi]

2016

JU_KS_Group@FIRE 2016: Consumer Health Information SearchKamal Sarkar, Debanjan Das, Indra Banerjee, Mamta Kumari, Prasenjit Biswas. fire 2016: 208-213 [doi]

2010

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platformPrasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan. samos 2010: 265-272 [doi]

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable PlatformPrasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan. isvlsi 2010: 161-166 [doi]

2009

2000

SH-5: The 64-Bit SuperH ArchitecturePrasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama. micro, 20(4):28-39, 2000. [doi]

1997

Functional verification of the superscalar SH-4 microprocessorPrasenjit Biswas, Andy Freeman, Kouji Yamada, Norio Nakagawa, Kunio Uchiyama. compcon 1997: 115-120 [doi]

1995

SH3: high code density, low powerAtsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas. micro, 15(6):11-19, 1995. [doi]

1994

Cut and Side-Effects in a Data-Driven Implementation of PrologSurapong Auwatanamongkol, Andrzej Ciepielewski, Prasenjit Biswas. ngc, 12(3):223-250, 1994.

1993

An extended scheduling technique for software pipeliningDagung Lu, Prasenjit Biswas. jsa, 37(1-5):99-103, 1993. [doi]

PARSA: A Parallel Program Scheduling and Assessment EnvironmentBehrooz Shirazi, Krishna M. Kavi, Ali R. Hurson, Prasenjit Biswas. icpp 1993: 68-72

1992

A memory-mapped interprocessor communication architecture using FIFO RAMsSyhy-Chang Su, Prasenjit Biswas. jsa, 34(1-5):187-191, 1992. [doi]

1991

A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic ProgramsSurapong Auwatanamongkol, Prasenjit Biswas. icpp 1991: 17-20

A snooping cache coherency protocol for hierarchically organized multiprocessorsGautam Dewan, Prasenjit Biswas. jsa, 31(1-5):105-111, 1991. [doi]

1990

A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machinesPrasenjit Biswas, Jin Chen. jsa, 28(1-5):161-166, 1990. [doi]

Scheduling demand-driven parallel logic programs on transputersShyh-Chang Su, Prasenjit Biswas. jsa, 28(1-5):37-41, 1990. [doi]

1989

Abstract machine LORAP II and experiments in process grain size determination for parallel execution of logic programsChin-Feng Fan, Prasenjit Biswas. ictai 1989: 685-692 [doi]

1988

A Scalable Abstract Machine Model to Support Limited-OR (LOR) / Restricted-AND Parallelism (RAP) in Logic ProgramsPrasenjit Biswas, Shyh-Chang Su, David Y. Y. Yun. ICLP 1988: 1160-1179

A Fuzzy Hybrid Model for Pattern ClassificationPrasenjit Biswas, Arun K. Majumdar. par 1988: 183-192

LogDf: A Data-Driven Abstract Machine Model for Parallel Execution of Logic ProgramsPrasenjit Biswas, Chien-Chao Tseng. fgcs 1988: 1059-1070

A Data-Driven Parallel Execution Model for Logic ProgramsChien-Chao Tseng, Prasenjit Biswas. ICLP 1988: 1204-1222

1985

Architectural support for variable addressing in Ada - A design approachPrasenjit Biswas, Subrata Dasgupta. ijpp, 14(1):51-72, 1985. [doi]

1983

A supervised learning algorithm for hierarchical classification of fuzzy patternsPrasenjit Biswas, Arun K. Majumdar. isci, 31(2):91-106, 1983. [doi]

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