Abstract is missing.
- European ICT Research: 2011-2012 Outlook for Components and SystemsPanagiotis Tsarchopoulos. 1-2 [doi]
- Digital Microfluidic Biochips: A Vision for Functional Diversity and More Than MooreKrishnendu Chakrabarty. 3-4 [doi]
- Small Worlds: The Dynamics of NoCs in Tomorrow SoC ArchitectureMarcello Coppola. 5 [doi]
- Reconfigurable Architectures for Bioinformatics ApplicationsApostolos Dollas. 6-7 [doi]
- Challenges and Perspectives of Computer Architecture at the Nano ScaleChristian Gamrat. 8-10 [doi]
- SUT-RNS Forward and Reverse ConvertersEvangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos. 11-16 [doi]
- Clock Tree Synthesis with XOR Gates for Polarity AssignmentJianchao Lu, Baris Taskin. 17-22 [doi]
- A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro CellsChristian Pilato, Fabrizio Ferrandi, Davide Pandini. 23-28 [doi]
- A BDD-Based Design of an Area-Power Efficient Asynchronous AdderGopal Paul, Rohit Reddy, Chittaranjan A. Mandal, Bhargab B. Bhattacharya. 29-34 [doi]
- Efficient Hardware Looping Units for FPGAsNikolaos Kavvadias, Konstantinos Masselos. 35-40 [doi]
- Exploration of 2D Cellular Automata as Binary Sequence GeneratorsEfthymia Arvaniti, Ilias Mavridis, Athanasios Kakarountas. 41-45 [doi]
- Fine-Grained Fault Tolerance for Process Variation-Aware CachesTayyeb Mahmood, Soontae Kim. 46-51 [doi]
- Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCTPrakash Srinivasan, Ronan Farrell. 52-57 [doi]
- Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGAFarid Lahrach, Abderrahim Doumar, Eric Chatelet, Abderrazek Abdaoui. 58-62 [doi]
- Self-Freeze Linear Decompressors for Low Power TestingVasileios Tenentes, Xrysovalantis Kavousianos. 63-68 [doi]
- Logical Core Algorithm: Improving Global PlacementFelipe Pinto, Lucas Cavalheiro, Marcelo de Oliveira Johann, Ricardo Reis. 69-73 [doi]
- Safety Aware Place and Route for On-Chip Redundancy in Safety Critical ApplicationsRomuald Girardey, Michael Hübner, Jürgen Becker. 74-79 [doi]
- Inter-process Communication Using Pipes in FPGA-Based Adaptive ComputingMing Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch. 80-85 [doi]
- Highly Efficient Transforms Module Solution for a H.264/SVC EncoderRonaldo Husemann, Mariano Majolo, Altamiro Amadeu Susin, Valter Roesler, José Valdeni de Lima. 86-91 [doi]
- Input-Output Selection Based Router for Networks-on-ChipMasoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 92-97 [doi]
- Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential ProgramsMichael F. Dossis. 98-103 [doi]
- Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned SearchingSotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos. 104-109 [doi]
- Adaptive Task Migration Policies for Thermal Control in MPSoCsDavid Cuesta, José L. Ayala, José Ignacio Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii. 110-115 [doi]
- A Scalable Bandwidth Aware Architecture for Connected Component LabelingVikram Sampath Kumar, Kevin M. Irick, Ahmed Al-Maashri, Narayanan Vijaykrishnan. 116-121 [doi]
- LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads SupportDavid Stevens, Vassilios Chouliaras. 122-126 [doi]
- A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy EfficiencyDaniel P. Volpato, Alexandre K. I. Mendonça, Luiz C. V. dos Santos, José Luís Güntzel. 127-132 [doi]
- Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip ArchitecturesIasonas Filippopoulos, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, George Economakos. 133-138 [doi]
- BLAKE HASH Function Family on FPGA: From the Fastest to the SmallestNicolas Sklavos, Paris Kitsos. 139-142 [doi]
- Differential Power Analysis of CAST-128Keanhong Boey, Yingxi Lu, Máire O Neill, Roger Woods. 143-148 [doi]
- QCA Systolic Matrix MultiplierLiang Lu, Weiqiang Liu, Máire O Neill, Earl E. Swartzlander Jr.. 149-154 [doi]
- Hardware Module Design for Ensuring TrustApostolos P. Fournaris. 155-160 [doi]
- Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable PlatformPrasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan. 161-166 [doi]
- Task Dispersal Measurement in Dynamic Reconfigurable NoCsMohammad Hosseinabady, Jose Luis Nunez-Yanez, Antonio Marcello Coppola. 167-172 [doi]
- Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale CrossbarsBehnam Ghavami, Alireza Tajary, Mohsen Raji, Hossein Pedram. 173-178 [doi]
- ASIC Design of an Adaptive Control Unit for Reconfigurable Analog-to-Digital ConvertersZulhakimi Razak, Ahmet T. Erdogan, Tughrul Arslan. 179-184 [doi]
- A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal ProcessingSalwa Mostafa, Wenchao Qu, Syed K. Islam, Mohamed Mahfouz. 185-189 [doi]
- Fast Sequential FPGA Startup Based on Partial and Dynamic ReconfigurationMichael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart. 190-194 [doi]
- A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-ImmunityMehrdad Khatir, Alireza Ejlali. 195-200 [doi]
- Memory-Less Pipeline Dynamic Circuit Design TechniqueThemistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas. 201-205 [doi]
- A Floating Gate MOSFET Based Current Reference with Subtraction TechniqueV. Suresh Babu, P. S. Haseena, M. R. Baiju. 206-209 [doi]
- A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOSSamuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula. 210-215 [doi]
- Pattern-Driven Clock Tree Routing with Via MinimizationAli M. Farhangi, Asim J. Al-Khalili, Dhamin Al-Khalili. 216-221 [doi]
- Ultra-Low-Power Sensor Signal Monitoring and Impulse Radio Architecture for Biomedical ApplicationsMohammad Rafiqul Haider, Ashraf B. Islam, Syed Kamrul Islam. 222-227 [doi]
- Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICsAnkit More, Baris Taskin. 228-231 [doi]
- Testing Parametric and Catastrophic Faults in Mixed-Signal Integrated Circuits Using WaveletsAlexios Spyronasios, Michael Dimopoulos, Nikolaos P. Papadopoulos, Alkis A. Hatzopoulos. 232-237 [doi]
- A Receiver Circuit for Low-Swing Interconnect SchemesYiannis Moisiadis, Yiorgos Tsiatouhas. 238-241 [doi]
- An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer DivisionNikos Petrellis, Michael K. Birbas, John C. Kikidis, Alexios N. Birbas. 242-246 [doi]
- DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold OperationKapil K. Rajput, Anil K. Saini, Subash C. Bose. 247-252 [doi]
- Fast Evaluation of Analog Circuits Using Linear ProgrammingZach Cashero, Allen Chen, Ryan Hoppal, Tom Chen. 253-258 [doi]
- FGMOS Based Built-In Current Sensor for Low Supply Voltage Analog and Mixed-Signal Circuits TestingStylianos Siskos. 259-264 [doi]
- A Sub-1μA Low-Power FSK Modulator for Biomedical Sensor CircuitsKai Zhu, Mohammad Rafiqul Haider, Song Yuan, Syed Kamrul Islam. 265-268 [doi]
- Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS TechnologyE. Vilella, Ángel Diéguez. 269-272 [doi]
- Low Power Single Electron Or/Nor Gate Operating at 10GHzThomas Tsiolakis, George Alexiou, Nikolaos Konofaos. 273-276 [doi]
- Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-MaterialZhou Hailiang, Zhang Minxuan, Fang Liang, Hao Yue. 277-281 [doi]
- A Mesh-Buffer Displacement Optimization StrategyGuilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis. 282-287 [doi]
- BLAS Comparison on FPGA, CPU and GPUSrinidhi Kestur, John D. Davis, Oliver Williams. 288-293 [doi]
- Reliability Analysis and Improvement in Nano Scale DesignMahtab Niknahad, Michael Hübner, Jürgen Becker. 299-303 [doi]
- Reliability-Aware Dynamic Voltage and Frequency ScalingFarshad Firouzi, Mostafa E. Salehi, Fan Wang, Sied Mehdi Fakhraie, Saeed Safari. 304-309 [doi]
- TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag ArrayShuai Wang, Jie S. Hu, Sotirios G. Ziavras. 310-315 [doi]
- A Delay Model of Two-Cycle NoC Router in 2D-Mesh NetworkShubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang. 316-320 [doi]
- Tree-Based Routing for Faulty On-Chip Networks with Mesh TopologyHsin-Chou Chi, Yu-Hong Jhang, Wen-Shu Chen. 321-326 [doi]
- A Hierarchical Hybrid Optical-Electronic Network-on-ChipMo Kwai Hung, Yaoyao Ye, Xiaowen Wu, Wei Zhang, Weichen Liu, Jiang Xu. 327-332 [doi]
- A High Throughput Low Power FIFO Used for GALS NoC BuffersMohammad Fattah, Abdurrahman Manian, Abbas Rahimi, Siamak Mohammadi. 333-338 [doi]
- An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCsElena Kakoulli, Vassos Soteriou, Theocharis Theocharides. 339-344 [doi]
- A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined RadioCamille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres. 345-350 [doi]
- Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication ArchitectureUlhas Deshmukh, Vineet Sahula. 351-356 [doi]
- Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware ModelNaoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu. 357-362 [doi]
- An Analytical Framework with Bounded Deflection Adaptive Routing for Networks-on-ChipPavel Ghosh, Arvind Ravi, Arunabha Sen. 363-368 [doi]
- Hybrid QoS Method for Networks-on-ChipShijun Lin, Jianghong Shi, Huihuang Chen. 369-374 [doi]
- XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy EvaluationTheodoros Lioris, Grigoris Dimitroulakos, Kostas Masselos. 375-380 [doi]
- Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Fault Detection and RepairR. K. Sharma, Aditi Sood. 381-386 [doi]
- A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory InterfaceAlexis Alexandropoulos, Efthimios Davrazos, Fotis Plessas, Michael K. Birbas. 387-392 [doi]
- Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM ArraysTaniya Siddiqua, Sudhanva Gurumurthi. 393-398 [doi]
- A New Low-Power Soft-Error Tolerant SRAM CellNicholas Axelos, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos. 399-404 [doi]
- The Impact of Process Faults on Specific Parameters of a 1.9GHz CMOS MixerAnastasios Karagounis, Basilis Kotsos, Nikolaos Assimakis, Eyrikleia Petropoulou, Athanasios Polyzos. 405-409 [doi]
- Improved Yield in Nanotechnology Circuits Using Non-square MeshesCostas Argyrides, Nikolaos Mavrogiannakis, Dhiraj K. Pradhan. 410-415 [doi]
- Dynamic Power Management on LDPC DecodersErick Amador, Raymond Knopp, Vincent Rezard, Renaud Pacalet. 416-421 [doi]
- Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-TheoryImen Mansouri, Camille Jalier, Fabien Clermidy, Pascal Benoit, Lionel Torres. 422-427 [doi]
- Data-Flow Driven Equivalence Checking for Verification of Code Motion TechniquesChandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal. 428-433 [doi]
- A Novel, Variable Resolution Flash ADC with Sub Flash ArchitectureMahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 434-435 [doi]
- Bitstream Efficiency of Field Programmable One-Hot ArraysMark G. Arnold, Panagiotis D. Vouzis, Jung H. Cho. 436-441 [doi]
- A Family of Area-Time Efficient Modulo 2n+1 AddersHaridimos T. Vergos. 442-443 [doi]
- A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple VddKostas Siozios, Iraklis Anagnostopoulos, Dimitrios Soudris. 444-445 [doi]
- Towards Supporting Fault-Tolerance in FPGAsKostas Siozios, Dimitrios Soudris, Dionisios N. Pnevmatikatos. 446-447 [doi]
- Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area OverheadUsha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta. 448-449 [doi]
- A Novel On-Chip Interconnection Topology for Mesh-Connected Processor ArraysXiaofang Wang. 450-451 [doi]
- BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical ChannelsAmir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 452-453 [doi]
- Generation and Exploration of Layouts for Area-Efficient Barrel ShiftersAlen Bardizbanyan, Kasyab P. Subramaniyan, Per Larsson-Edefors. 454-455 [doi]
- A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRCAmir Sabbagh Molahosseini, Keivan Navi. 456-457 [doi]
- Impact of Process Variations on Flip-Flops Energy and Timing CharacteristicsMarco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello. 458-459 [doi]
- Side Channel Attacks Cryptanalysis against Block Ciphers Based on FPGA DevicesAnestis Bechtsoudis, Nicolas Sklavos. 460-461 [doi]
- Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation TechniqueXiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu. 462-463 [doi]
- Autonomous Design in VLSI: An In-House Universal Cellular Neural PlatformLudovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras. 464-466 [doi]
- High-Performance TSV Architecture for 3-D ICsMasoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 467-468 [doi]
- Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGARomuald Girardey, Michael Hübner, Jürgen Becker. 469-470 [doi]
- Design Automation and Analysis of Resonant Rotary Clocking TechnologyVinayak Honkote. 471-472 [doi]
- System Level Design of Complex Hardware Applications Using ImpulseCGeorgia Kalogeridou, Nikolaos S. Voros, Konstantinos Masselos. 473-474 [doi]
- Two-Dimensional Dynamic Multigrained Reconfigurable HardwareLars Braun, Jürgen Becker. 475-476 [doi]
- FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing ApplicationsDiana Göhringer, Jürgen Becker. 477-478 [doi]
- Performance Analysis of 3D NoCs Partitioning MethodsMasoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen. 479-480 [doi]
- Autonomous Design in VLSI: Growing and Learning on SiliconLudovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras. 481-485 [doi]
- High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor ArchitecturesSotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos. 486-487 [doi]
- MULTICUBE: Multi-objective Design Space Exploration of Multi-core ArchitecturesCristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Zhang Hao, Shibin Tang. 488-493 [doi]
- 2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core ArchitecturesCristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout. 494-499 [doi]
- System Level Design for Embedded Reconfigurable Systems Using MORPHEUS PlatformPaul Brelet, Arnaud Grasset, Philippe Bonnot, Frank Ieromnimon, Dimitrios Kritharidis, Nikolaos S. Voros. 500-505 [doi]
- The SATURN Approach to SysML-Based HW/SW CodesignWolfgang Müller 0003, Da He, Fabian Mischkalla, Arthur Wegele, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda. 506-511 [doi]
- Mapping Embedded Applications on MPSoCs: The MNEMEE ApproachChristos Baloukas, Lazaros Papadopoulos, Dimitrios Soudris, Sander Stuijk, Olivera Jovanovic, Florian Schmoll, Daniel Cordes, Robert Pyka, Arindam Mallik, Stylianos Mamagkakis, François Capman, Séverin Collet, Nikolaos Mitas, Dimitrios Kritharidis. 512-517 [doi]
- Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART ApproachBernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin. 518-523 [doi]