Table of Contents

• Adaptive Multifunctional Circuits and Systems for Future Generations of Wireless CommunicationsAleksandar Tasic. 3-11 [doi]
• A Self-Tuning Analog Proportional-Integral-Derivative (PID) ControllerVarun Aggarwal, Meng Mao, Una-May O Reilly. 12-19 [doi]
• A Tuning Technique for Switched-Capacitor CircuitsMustafa Keskin, Nurcan Keskin. 20-23 [doi]
• A Background Mismatch Calibration For Capacitive Digitial-To-Analog Converters RTERSMustafa Keskin. 24-27 [doi]
• Temperature-Adaptive Circuits on Reconfigurable Analog ArraysAdrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Rajeshuni Ramesham, Joseph Neff, Srinivas Katkoori. 28-31 [doi]
• A Modular Framework for the Evolution of Circuits on Configurable Transistor Array ArchitecturesMartin Trefzer, Jörg Langeheine, Karlheinz Meier, Johannes Schemmel. 32-42 [doi]
• Adaptive Micro-Antenna on Silicon SubstrateNakul Haridas, Ahmet T. Erdogan, Tughrul Arslan, Mark Begbie. 43-50 [doi]
• Using Hardware-Based Particle Swarm Method for Dynamic Optimization of Adaptive Array AntennasGabriella Kókai, Tonia Christ, Hans Holm Frühauf. 51-58 [doi]
• Systolic Array Based Adaptive Beamformer Modeling in SystemC EnvironmentOzgur Tamer, Ahmet Özkurt. 59-66 [doi]
• Automatic Alignment of Multiple Optical Components Using Genetic AlgorithmHirokazu Nosato, Masahiro Murakawa, Tetsuya Higuchi. 67-73 [doi]
• Woofer-Tweeter Adaptive Optics Test BenchOnur Keskin, Peter Hampton, Rodolphe Conan, Colin Bradley, Aaron Hilton, Celia Blain. 74-80 [doi]
• Switchable Glass: A Possible Medium for Evolvable HardwareMihai Oltean. 81-87 [doi]
• Evolvable Hardware Applied to NanotechnologyOmar Paranaiba Vilela Neto, Leone Pereira Masiero, Marco Aurélio Cavalcanti Pacheco, Carlos R. Hall Barbosa. 88-96 [doi]
• The Novel Stochastic Bernstein Method of Functional ApproximationJoseph Kolibal, Daniel Howard. 97-100 [doi]
• An Adaptive Heuristic Filter for AccelerationHoria-Nicolai L. Teodorescu. 101-108 [doi]
• Power Driven Reconfigurable Complex Continuous Wavelet TransformNizamettin Aydin, Tughrul Arslan. 109-113 [doi]
• Self-Configurable Neural Network Processor for FIR Filter ApplicationsGorn Tepvorachai, Christos A. Papachristou. 114-121 [doi]
• A New State Space Representation Method for Adaptive Log Domain SystemsRemzi Arslanalp, Abdullah T. Tola. 122-128 [doi]
• Hardware/Software Coevolution of Genome Programs and Cellular ProcessorsGianluca Tempesti, Pierre-André Mudry, Guillaume Zufferey. 129-136 [doi]
• Gene Regulation Mechanisms Introduced in the Evaluation Criteria for a Hardware Cellular Development SystemGunnar Tufte. 137-144 [doi]
• Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAsJustin Lee, Joaquin Sitte. 145-152 [doi]
• Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAsAndres Upegui, Eduardo Sanchez. 153-162 [doi]
• Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable HardwareJorge Peña, Andres Upegui, Eduardo Sanchez. 163-170 [doi]
• Evolutionary Design of Digital Circuits: Where Are Current Limits?Lukás Sekanina. 171-178 [doi]
• Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array StructuresEmanuele Stomeo, Tatiana Kalganova, Cyrille Lambert. 179-185 [doi]
• Evolution of Multifunctional Combinational Modules Controlled by the Power Supply VoltageLukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek. 186-193 [doi]
• Designing Electronic Circuits by Means of Gene Expression ProgrammingXuesong Yan, Wei Wei, Rui Liu, Sanyou Y. Zeng, Lishan Kang. 194-199 [doi]
• Genetic Algorithm based Engine for Domain-Specific Reconfigurable ArraysWing On Fung, Tughrul Arslan, Sami Khawam. 200-206 [doi]
• Towards the Integration of Drive Control Loop Electronics of the JPL/Boeing Gyroscope within an Autonomous Robust Custom-Reconfigurable PlatformEvangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson. 207-214 [doi]
• An Efficient Multi-Objective Evolutionary Algorithm for Combinational Circuit DesignRui Liu, Sanyou Y. Zeng, Lixin X. Ding, Lishan Kang, Hui Li, Yuping Chen, Yong Liu, Yueping Han. 215-221 [doi]
• Hardware Accelerators for Evolving Building Block Modules for Artificial BrainsHugo de Garis. 222-224 [doi]
• An Adaptive FPGA-Based Mechatronic Control System Supporting Partial Reconfiguration of Controller FunctionalitiesSteffen Toscher, Thomas Reinemann, Roland Kasper. 225-228 [doi]
• Reconfigurable Parallel Computing Architecture for On-Board Data ProcessingMohsin A. Syed, Eberhard Schüler. 229-236 [doi]
• Population-Based FPGA Solution to Mastermind GameH. Fatih Ugurdag, Yahya Sahin, Onur Baskirt. 237-246 [doi]
• Adaptable Architectures for Signal Processing ApplicationsMartin Margala. 247-254 [doi]
• The Gannet Service-Based SoC: A Service-level Reconfigurable ArchitectureWim Vanderbauwhede. 255-261 [doi]
• On-Board Partial Run-Time Reconfiguration for Pico-Satellite ConstellationsTanya Vladimirova, Xiaofeng Wu. 262-269 [doi]
• Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression TechniquesSajid Baloch, Tughrul Arslan, Adrian Stoica. 270-280 [doi]
• A Honeycomb Development Architecture for Robust Fault-Tolerant DesignAndy M. Tyrrell, Hong Sun. 281-287 [doi]
• Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial ReconfigurationKatarina Paulsson, Michael Hübner, Jürgen Becker. 288-291 [doi]
• An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable ArchitecturesSajid Baloch, Tughrul Arslan, Adrian Stoica. 292-295 [doi]
• Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature ElectronicsDidier Keymeulen, Ricardo Salem Zebulum, Rajeshuni Ramesham, Adrian Stoica, Srinivas Katkoori, Sharon Graves, Frank Novak, Charles Antill. 296-300 [doi]
• A FPGA Simulation Using Asexual Genetic Algorithms for Integrated Self-RepairRobert Ross, Richard Hall. 301-304 [doi]
• SW-HW Co-design and Fault Tolerant Implementation for the LRID Wireless Communication SystemStefanos Skoulaxinos. 305-308 [doi]
• Analytical Modelling of Power Attenuation under Parameter Fluctuations with Applications to Self-Test and RepairH. J. Kadim. 309-312 [doi]
• An Automatic Technique to Synthesize Avionics ArchitectureSavio Chau, Van Dang, Joseph Xu, James Lu. 313-316 [doi]
• State-Space Based Analytical Modelling for Real-Time Fault Recovery and Self-Repair with Applications to BiosensorsH. J. Kadim. 317-322 [doi]
• ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace-Based Monitoring and DiagnosticsTughrul Arslan, Nakul Haridas, Erfu Yang, Ahmet T. Erdogan, Nick Barton, A. J. Walton, John S. Thompson, Adrian Stoica, Tanya Vladimirova, Klaus D. McDonald-Maier, W. Gareth J. Howells. 323-329 [doi]
• Enabling Technologies for Distributed Picosatellite Missions in LEOTanya Vladimirova, Xiaofeng Wu, Kawsu Sidibeh, David Barnhart, Abdul-Halim Jallad. 330-337 [doi]
• A Generic On-Chip Debugger for Wireless Sensor NetworksAndrew B. T. Hopkins, Klaus D. McDonald-Maier. 338-342 [doi]
• Novel Techniques for Ensuring Secure Communications for Distributed Low Power DevicesGareth Howells, Evangelos Papoutsis, Klaus D. McDonald-Maier. 343-350 [doi]
• GEZGIN & GEZGIN-2: Adaptive Real-Time Image Processing Subsystems for Earth Observing Small SatellitesA. Neslin Ismailoglu, O. Benderli, Soner Yesil, Refik Sever, Burak Okcan, O. Sengul, Rusen Öktem. 351-358 [doi]
• A Comparative Design of Satellite Attitude Control System with Reaction WheelShengmin Ge, Hao Cheng. 359-364 [doi]
• Towards Fluent Sensor Networks: A Scalable and Robust Self-Deployment ApproachMuhammed R. Pac, Aydan M. Erkmen, Ismet Erkmen. 365-372 [doi]
• On-Chip Evolution Using a Soft Processor Core Applied to Image RecognitionKyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yoshiki Yamaguchi. 373-380 [doi]
• An Efficient Hardware Architecture for H.264 Adaptive Deblocking FilterMustafa Parlak, Ilker Hamzaoglu. 381-385 [doi]
• An FPGA Implemented Processor Architecture with Adaptive ResolutionJim Torresen, Jonas Jakobsen. 386-389 [doi]
• Automatic Hybrid Genetic Algorithm Based Printed Circuit Board InspectionSyamsiah Mashohor, Jonathan R. Evans, Ahmet T. Erdogan. 390-400 [doi]
• Routing in Wireless Sensor Networks Using Ant Colony OptimizationSelcuk Okdem, Dervis Karaboga. 401-404 [doi]
• Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoCBalal Ahmad, Ahmet T. Erdogan, Sami Khawam. 405-411 [doi]
• A Novel Self-Organizing Hybrid Network Protocol for Wireless Sensor NetworksJichuan Zhao, Ahmet T. Erdogan. 412-419 [doi]
• Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC)Ioannis Nousias, Tughrul Arslan. 420-423 [doi]
• A Multi-Objective Genetic Algorithm for On-Chip Real-time Adaptation of a Multi-Carrier Based Telecommunications ReceiverNasri Sulaiman, Ahmet T. Erdogan. 424-427 [doi]
• A Low-Complexity Self-Calibrating Adaptive Quadrature ReceiverEdiz Çetin, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling. 428-435 [doi]
• Design Concepts for a Dynamically ReconfigurableWireless Sensor NodeHeiko Hinkelmann, Peter Zipf, Manfred Glesner. 436-441 [doi]
• On the Trellis Structures of Geometric Augmented Product CodesGökmen Altay, Osman N. Uçan, Nejla Altay, Senay Yalçin. 442-450 [doi]
• Protecting Fingerprint Data Using WatermarkingKhalil Zebbiche, Lahouari Ghouti, Fouad Khelifi, Ahmed Bouridane. 451-456 [doi]
• Finite State Machine IP Watermarking: A TutorialAmr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid. 457-464 [doi]
• Face Recognition Using a Gabor Filter Bank ApproachWalid R. Boukabou, Lahouari Ghouti, Ahmed Bouridane. 465-468 [doi]
• VLSI Design IP Protection: Solutions, New Challenges, and OpportunitiesLin Yuan, Gang Qu, Lahouari Ghouti, Ahmed Bouridane. 469-476 [doi]
• A Large Scale Adaptable Multiplier for Cryptographic ApplicationsOsama Al-Khaleel, Christos A. Papachristou, Frank Wolff, Kiamal Z. Pekmestzi. 477-484 [doi]