Zdenek Kotásek - researchr alias

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Viewing Publication 1 - 84 from 84

2021

Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAsJakub Lojda, Richard Panek, Zdenek Kotásek. dsd 2021: 549-552 [doi]

Reliability Analysis of the FPGA Control System with Reconfiguration HardeningRichard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek. dsd 2021: 553-556 [doi]

2020

Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack ProblemJakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek. ddecs 2020: 1-4 [doi]

Hardening of Smart Electronic Lock Software against Random and Deliberate FaultsJakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek. dsd 2020: 680-683 [doi]

Analysis of Software-Implemented Fault Tolerance: Case Study on Smart LockJakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek. ewdts 2020: 1-5 [doi]

Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case StudyRichard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek. vlsi-dat 2020: 1-4 [doi]

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection DeterminationJakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek. lascas 2020: 1-4 [doi]

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic LocksJakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek. lascas 2020: 1-4 [doi]

2019

Testing Reliability of Smart Electronic Locks: Analysis and the First Steps TowardsOndrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek. dsd 2019: 506-513 [doi]

Detecting hard synapses faults in artificial neural networksMartin Krcma, Zdenek Kotásek, Jakub Lojda. latw 2019: 1-6 [doi]

Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA SystemsJakub Lojda, Jakub Podivinsky, Zdenek Kotásek. latw 2019: 1-4 [doi]

Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot ControllerJakub Podivinsky, Jakub Lojda, Zdenek Kotásek. latw 2019: 1-4 [doi]

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case StudyJakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek. dsd 2019: 597-600 [doi]

Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault RecoveryKarel Szurman, Zdenek Kotásek. latw 2019: 1-4 [doi]

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430Karel Szurman, Zdenek Kotásek. ddecs 2019: 1-4 [doi]

2018

Program Generation Through a Probabilistic Constrained GrammarOndrej Cekan, Jakub Podivinsky, Zdenek Kotásek. dsd 2018: 214-220 [doi]

Input and Output Generation for the Verification of ALU: A Use CaseOndrej Cekan, Richard Panek, Zdenek Kotásek. ewdts 2018: 1-6 [doi]

FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design AutomationJakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek. dsd 2018: 244-251 [doi]

Fault Tolerance Properties of Systems Generated with the Use of High-Level SynthesisJakub Lojda, Jakub Podivinsky, Zdenek Kotásek. ewdts 2018: 1-7 [doi]

Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based EvaluationRichard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek. ewdts 2018: 1-6 [doi]

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot ControllerJakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek. dsd 2018: 229-236 [doi]

A Processor Optimization Framework for a Selected ApplicationJalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek. ewdts 2018: 1-11 [doi]

An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot ControllerJakub Podivinsky, Jakub Lojda, Zdenek Kotásek. ewdts 2018: 1-7 [doi]

2017

A Probabilistic Context-Free Grammar Based Random Test Program GenerationOndrej Cekan, Zdenek Kotásek. dsd 2017: 356-359 [doi]

Triple modular redundancy used in field programmable neural networksMartin Krcma, Zdenek Kotásek, Jakub Lojda. ewdts 2017: 1-6 [doi]

Comparison of FPNNs models approximation capabilities and FPGA resources utilizationMartin Krcma, Zdenek Kotásek, Jakub Lojda. iccp2 2017: 125-132 [doi]

Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluationJakub Lojda, Jakub Podivinsky, Zdenek Kotásek. ewdts 2017: 1-6 [doi]

Data types and operations modifications: A practical approach to fault tolerance in HLSJakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma. ewdts 2017: 1-6 [doi]

Functional verification based platform for evaluating fault tolerance propertiesJakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek. mam, 52:145-159, 2017. [doi]

Reliability Analysis and Improvement of FPGA-Based Robot ControllerJakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek. dsd 2017: 337-344 [doi]

2016

Random stimuli generation based on a stochastic context-free grammarOndrej Cekan, Jakub Podivinsky, Zdenek Kotásek. fpt 2016: 295-296 [doi]

Implementation of fault tolerant techniques into FPNNsMartin Krcma, Zdenek Kotásek, Jakub Lojda. fpt 2016: 297-298 [doi]

HLS-based fault tolerance approach for SRAM-based FPGAsJakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek. fpt 2016: 301-302 [doi]

Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical SystemsJakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek. dsd 2016: 487-494 [doi]

Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAsJakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek. fpt 2016: 293-294 [doi]

Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability AnalysisMarcela Zachariaova, Michaela Kekelyova-Beleova, Zdenek Kotásek. dsd 2016: 380-387 [doi]

2015

Application of Evolutionary Algorithms for Regression Suites OptimizationMichaela Beleova, Zdenek Kotásek, Marcela imkova, Toma Hruka. ddecs 2015: 91-94 [doi]

Software Fault Tolerance: The Evaluation by Functional VerificationOndrej Cekan, Jakub Podivinsky, Zdenek Kotásek. dsd 2015: 284-287 [doi]

Automation and Optimization of Coverage-driven VerificationMarcela imkova, Zdenek Kotásek. dsd 2015: 87-94 [doi]

Fault tolerant Field Programmable Neural NetworksMartin Krcma, Zdenek Kotásek, Jan Kastil. norchip 2015: 1-4 [doi]

Mapping Trained Neural Networks to FPNNsMartin Krcmár, Jan Kastil, Zdenek Kotásek. ddecs 2015: 157-160 [doi]

FPGA Prototyping and Accelerated Verification of ASIPsJakub Podivinsky, Marcela imkova, Ondrej Cekan, Zdenek Kotásek. ddecs 2015: 145-148 [doi]

The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applicationsJakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek. mam, 39(8):1215-1230, 2015. [doi]

2014

2013

2012

2011

Decreasing test time by scan chain reorganizationPavel Bartos, Zdenek Kotásek, Jan Dohnal. ddecs 2011: 371-374 [doi]

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant SystemsMartin Straka, Jan Kastil, Zdenek Kotásek. dsd 2011: 223-230 [doi]

Advanced fault tolerant bus for multicore system implemented in FPGAMartin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek. ddecs 2011: 397-398 [doi]

2010

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power ConsumptionZdenek Kotásek, Jaroslav Skarvada, Josef Strnadel. dsd 2010: 644-651 [doi]

Reduction of power dissipation through parallel optimization of test vector and scan register sequencesZdenek Kotásek, Jaroslav Skarvada, Josef Strnadel. ddecs 2010: 364-369 [doi]

The Use of Genetic Algorithm to Reduce Power Consumption during Test ApplicationJaroslav Skarvada, Zdenek Kotásek, Josef Strnadel. ices 2010: 181-192 [doi]

Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic ReconfigurationMartin Straka, Jan Kastil, Zdenek Kotásek. dsd 2010: 365-372 [doi]

Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAsMartin Straka, Jan Kastil, Zdenek Kotásek. ddecs 2010: 173-176 [doi]

2008

2007

2006

FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic PropertiesTomas Pecenka, Zdenek Kotásek, Lukás Sekanina. ddecs 2006: 285-289

Testability Estimation Based on Controllability and Observability ParametersTomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina. dsdm 2006: 504-514 [doi]

Evolution of Multifunctional Combinational Modules Controlled by the Power Supply VoltageLukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek. ahs 2006: 186-193 [doi]

Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational ModulesLukás Sekanina, Lukás Starecek, Zdenek Kotásek. ddecs 2006: 85-86

SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded SystemJosef Strnadel, Zdenek Kotásek. ECBS 2006: 497-498 [doi]

2005

Automatic Discovery of RTL Benchmark Circuits with Predefined Testability PropertiesTomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel. ehci 2005: 51-58 [doi]

Educational Tool for the Demonstration of DfT Principles Based on Scan MethodologiesJosef Strnadel, Zdenek Kotásek. dsdm 2005: 420-427 [doi]

2003

Test scheduling for embedded systemsZdenek Kotásek, Daniel Mika, Josef Strnadel. dsdm 2003: 463-467 [doi]

2002

Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT LevelJosef Strnadel, Zdenek Kotásek. dsdm 2002: 166-173 [doi]

2000

Formal Approach to the RTL Testability AnalysisZdenek Kotásek, Richard Ruzicka, Jan Hlavicka. latw 2012: 256-261

1997

RT Level Test SchedulingJ. Blatný, Zdenek Kotásek, Jan Hlavicka. cai, 16(1):13-29, 1997.

RT level testability analysis to reduce test application timeZdenek Kotásek, F. Zboril. euromicro 1997: 104 [doi]

1995

I-Path AnalysisJ. Blatný, Zdenek Kotásek. cai, 14(5):513-530, 1995.

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2021

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1995

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