Abstract is missing.
- Optimization of Area and Delay at Gate-Level in Multiple Constant MultiplicationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. 3-10 [doi]
- Visualization of Multi-objective Design Space Exploration for Embedded SystemsToktam Taghavi, Andy D. Pimentel. 11-20 [doi]
- Design of Trace-Based Split Array Caches for Embedded ApplicationsAlice M. Tokarnia, Marina Tachibana. 21-27 [doi]
- Software Programmable Data Allocation in Multi-bank Memory of SIMD ProcessorsJian Wang, Joar Sohl, Olof Kraigher, Dake Liu. 28-33 [doi]
- An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on ChipMaurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania. 37-44 [doi]
- Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive RoutingNastaran Salehi, Ahmad Khadem Zadeh, Arash Dana. 45-52 [doi]
- NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS SystemsTim Kranich, Mladen Berekovic. 53-59 [doi]
- A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip NetworksSon Truong Nguyen, Shigeru Oyanagi. 60-67 [doi]
- Reconfigurable Grid Alu Processor: Optimization and Design Space ExplorationBasher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer. 71-79 [doi]
- Creation of Partial FPGA Configurations at Run-TimeMiguel Lino Silva, Joao Canas Ferreira. 80-87 [doi]
- A Modular Peripheral to Support Self-Reconfiguration in SoCsAndrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo. 88-95 [doi]
- High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAsRuben Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina. 96-103 [doi]
- Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow ApplicationsKees G. W. Goossens, Dongrui She, Aleksandar Milutinovic, Anca Mariana Molnos. 107-114 [doi]
- A Markov Model for Low-Power High-Fidelity Design-Space ExplorationJing Cao, Albert Nymeyer. 115-122 [doi]
- A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC DecoderF. Pescador, E. Juarez, D. Samper, C. Sanz, Mickaël Raulet. 123-129 [doi]
- On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric ChannelsStanislaw J. Piestrak. 133-140 [doi]
- QoR Analysis of Automated Clock-Mesh Implementation under OCV ConsiderationDennis Bode, Mladen Berekovic, Axel Borkowski, Ludger Buker. 141-146 [doi]
- A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital SystemsSameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai. 147-154 [doi]
- Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong ConstraintsIgor Lemberski, Petr Fiser. 155-162 [doi]
- A Latency-Efficient Router Architecture for CMP SystemsAntoni Roca, Jose Flich, Federico Silla, José Duato. 165-172 [doi]
- Trading Hardware Overhead for Communication Performance in Mesh-Type TopologiesClaas Cornelius, Philipp Gorski, Stephan Kubisch, Dirk Timmermann. 173-180 [doi]
- Designing Efficient Source Routing for Mesh Topology Network on Chip PlatformsSaad Mubeen, Shashi Kumar. 181-188 [doi]
- Evaluating OpenMP Support Costs on MPSoCsAndrea Marongiu, Paolo Burgio, Luca Benini. 191-198 [doi]
- Re-NUCA: Boosting CMP Performance Through Block ReplicationPierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, Giovanna Monni. 199-206 [doi]
- Filtering Directory Lookups in CMPsAna Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería. 207-216 [doi]
- Low Latency Recovery from Transient Faults for Pipelined Processor ArchitecturesMarcus Jeitler, Jakob Lechner. 219-225 [doi]
- RobuCheck: A Robustness Checker for Digital CircuitsStefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler. 226-231 [doi]
- Dynamic Control Flow Checking Technique for Reliable MicroprocessorsMakoto Sugihara. 232-239 [doi]
- Arithmetic Units for RNS Moduli {2n-3} and {2n+3} OperationsPedro Miguel Matutino, Ricardo Chaves, Leonel Sousa. 243-246 [doi]
- Real-Time Testing of True Random Number Generators Through Dynamic ReconfigurationDan Hotoleanu, Octavian Cret, Alin Suciu, Tamas Györfi, Lucia Vacariu. 247-250 [doi]
- Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE ProfileSubayal Khan, Kari Tiensyrjä, Jari Nurmi. 251-254 [doi]
- An Improved Automotive Multiple Target Tracking System DesignTobias Lange, Naim Harb, Haisheng Liu, Smaïl Niar, Rabie Ben Atitallah. 255-258 [doi]
- Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-ResolutionLara G. Villanueva, Gustavo Marrero Callicó, Félix Tobajas, Sebastián López, Valentin de Armas, José Francisco López, Roberto Sarmiento. 259-262 [doi]
- Generated Cycle-Accurate Profiler for C LanguageZdenek Prikryl, Karel Masarik, Tomas Hruska, Adam Husar. 263-268 [doi]
- Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network ApplicationsMostafa E. Salehi, Hamed Dorosti, Sied Mehdi Fakhraie. 269-272 [doi]
- Simulation of High-Performance Memory AllocatorsJosé Luis Risco-Martín, José Manuel Colmenar, David Atienza, José Ignacio Hidalgo. 275-282 [doi]
- Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan StructuresRené Kothe, Heinrich Theodor Vierhaus. 283-290 [doi]
- Exploration of Network Alternatives for Middleware-centric Embedded System DesignFranco Fummi, Giovanni Perbellini, Davide Quaglia, R. Trenti. 291-297 [doi]
- Adaptive Beamforming Using the Reconfigurable MONTIUM TPMarcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit. 301-308 [doi]
- A Common Operator for FFT and Viterbi AlgorithmsMalek Naoues, Laurent Alaus, Dominique Noguet. 309-313 [doi]
- ALOE-Based Flexible LDPC DecoderIsmael Gómez, Massimo Camatel, Jordi Bracke, Vuk Marojevic, Antoni Gelonch, Fabrizio Vacca, Guido Masera. 314-320 [doi]
- Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGAAdolfo Recio, Peter M. Athanas. 321-327 [doi]
- Adaptive Cache Memories for SMT ProcessorsSonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo. 331-338 [doi]
- Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications?Frank Reichenbach, Alexander Wold. 339-346 [doi]
- A Case for Hardware Task Management Support for the StarSS Programming ModelCor Meenderinck, Ben H. H. Juurlink. 347-354 [doi]
- On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable PlatformsGeorge Kornaros, Antonios Motakis. 355-362 [doi]
- Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic ReconfigurationMartin Straka, Jan Kastil, Zdenek Kotásek. 365-372 [doi]
- System Level Hardening by Computing with MatricesRonaldo Rodrigues Ferreira, Alvaro Freitas Moreira, Luigi Carro. 373-379 [doi]
- Faults Coverage Improvement Based on Fault Simulation and Partial DuplicationJaroslav Borecky, Martin Kohlik, Hana Kubatova, Pavel Kubalík. 380-386 [doi]
- A Class of Recursive Networks on a Chip for Enhancing Intercluster ParallelismMasaru Takesue. 389-392 [doi]
- A Programming Model and a NoC-Based Architecture for Streaming ApplicationsYun Jie Wu, Dominique Houzet, Sylvain Huet. 393-397 [doi]
- Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting CapabilitySomayyeh Koohi, Alireza Shafaei, Shaahin Hessabi. 398-403 [doi]
- Performance Analysis of 90nm Look Up Table (LUT) for Low Power ApplicationDeepak Kumar, Pankaj Kumar, Manisha Pattanaik. 404-407 [doi]
- Area-Efficient Multi-moduli Squarers for RNSDimitris Bakalis, Haridimos T. Vergos. 408-411 [doi]
- A Load-Forwarding Mechanism for the Vector Architecture in Multimedia ApplicationsYe Gao, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 412-415 [doi]
- Low Power FPGA Implementations of 256-bit Luffa Hash FunctionParis Kitsos, Nicolas Sklavos, Athanassios N. Skodras. 416-419 [doi]
- On the Numbers of Variables to Represent Multi-valued Incompletely Specified FunctionsTsutomu Sasao. 420-423 [doi]
- Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m)Somsubhra Talapatra, Hafizur Rahaman, Samir K. Saha. 427-432 [doi]
- An Improved Hardware Implementation of the Grain Stream CipherShohreh Sharif Mansouri, Elena Dubrova. 433-440 [doi]
- Description-Level Optimisation of Synthesisable Asynchronous CircuitsLuis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana. 441-448 [doi]
- A Parallel for Loop Memory Template for a High Level Synthesis CompilerCraig Moore, Wim Meeus, Harald Devos, Dirk Stroobandt. 449-455 [doi]
- In-channel Flow Control Scheme for Network-on-ChipVrishali Vijay Nimbalkar, Kuruvilla Varghese. 459-466 [doi]
- An Efficient Method to Reliable Data Transmission in Network-on-ChipsAhmad Patooghy, Hamed Tabkhi, Seyed Ghassem Miremadi. 467-474 [doi]
- Network-on-Multi-Chip (NoMC) for Multi-FPGA Multimedia SystemsMarta Stepniewska, Adam Luczak, Jakub Siast. 475-481 [doi]
- Persistence Management Model for Dynamically Reconfigurable HardwareJulio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Francisco Sanchez, Juan Carlos López. 482-489 [doi]
- System Level Synthesis for Ultra Low-Power Wireless Sensor NodesMuhammad Adeel Pasha, Steven Derrien, Olivier Sentieys. 493-500 [doi]
- A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol: Implementation and Experimental Validation over a Real-Time Operating systemRicardo Severino, Manish Batsa, Mário Alves, Anis Koubaa. 501-508 [doi]
- Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI EnvironmentsF. Lavratti, Alex R. Pinto, Leticia Maria Veiras Bolzani, Fabian Vargas, Carlos B. Montez, F. Hernandez, E. Gatti, C. Silva. 509-515 [doi]
- Path-Delay Fault Testing in Embedded Content Addressable MemoriesPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. 519-524 [doi]
- Application Dependent FPGA Testing MethodMartin Rozkovec, Jiri Jenícek, Ondrej Novák. 525-530 [doi]
- On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access MechanismXiao Zhang, Hans G. Kerkhoff, Bart Vermeulen. 531-537 [doi]
- Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power ConsumptionEnrique Barajas, Diego Mateo, José Luis González. 541-547 [doi]
- A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic BehaviourSander Stuijk, Marc Geilen, Twan Basten. 548-555 [doi]
- A Design Process for Hardware/Software System Co-design and its Application to Designing a Reconfigurable FPGAFélix Moreno, Ignacio López, Ricardo Sanz. 556-562 [doi]
- Optimising Self-Timed FPGA CircuitsPhillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume. 563-570 [doi]
- A New High-Level Methodology for Programming FPGA-Based Smart CameraNicolas Roudel, François Berry, Jocelyn Sérot, Laurent Eck. 573-578 [doi]
- Power Consumption Modeling for DVFS ExploitationAndrea Castagnetti, Cécile Belleudy, Sebastien Bilavarn, Michel Auguin. 579-586 [doi]
- Automated Power Characterization for Run-Time Power Emulation of SoC DesignsChristian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss, Josef Haid. 587-594 [doi]
- Customizable Composition and Parameterization of Hardware Design TransformationsTim Todman, Qiang Liu, Wayne Luk, George A. Constantinides. 595-602 [doi]
- Architectural Vulnerability Factor Estimation with Backwards AnalysisRobert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf. 605-612 [doi]
- Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic CircuitBibhash Sen, Anik Sengupta, Mamata Dalui, Biplab K. Sikdar. 613-620 [doi]
- Evaluation of RTD-CMOS Logic GatesJuan Núñez, Maria J. Avedillo, José M. Quintana. 621-627 [doi]
- On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor ApplicationsAllen Chen, Ryan Hoppal, Tom Chen. 628-634 [doi]
- A Formal Condition to Stop an Incremental Automatic Functional DiagnosisLuca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso. 637-643 [doi]
- The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power ConsumptionZdenek Kotásek, Jaroslav Skarvada, Josef Strnadel. 644-651 [doi]
- Multiple Bit Error Detection and Correction in MemoryJ. F. Tarillo, N. Mavrogiannakis, Carlos Arthur Lang Lisbôa, Costas Argyrides, Luigi Carro. 652-657 [doi]
- Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital CircuitsDmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. 658-663 [doi]
- Design Methodology for a High Performance Robust DVB-S2 Decoder ImplementationFlorent Berthelot, François Charot, Charles Wagner, Christophe Wolinski. 667-674 [doi]
- Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore ProcessorMuhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors. 675-680 [doi]
- A Memetic Approach for Nanoscale Hybrid Circuit Cell MappingZhufei Chu, Yinshui Xia, William N. N. Hung, Lun-Yao Wang, Xiaoyu Song. 681-688 [doi]
- Static Average Case Power Estimation Technique for Block CiphersTingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens. 689-696 [doi]
- An Approximate Maximum Common Subgraph Algorithm for Large Digital CircuitsJochem H. Rutgers, Pascal T. Wolkotte, Philip K. F. Hölzenspies, Jan Kuper, Gerard J. M. Smit. 699-705 [doi]
- Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory AnalysisSana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. 706-713 [doi]
- C?aSH: Structural Descriptions of Synchronous Hardware Using HaskellChristiaan Baaij, Matthijs Kooijman, Jan Kuper, Arjan Boeijink, Marco Gerards. 714-721 [doi]
- Storage-Aware Value PredictionMohammad Salehi, Amirali Baniasadi. 722-728 [doi]
- Computation Reduction Techniques for Vector Median Filtering and their Hardware ImplementationOzgur Tasdizen, Ilker Hamzaoglu. 731-736 [doi]
- A Novel VLSI Architecture of Fixed-Complexity Sphere DecoderBin Wu, Guido Masera. 737-744 [doi]
- A Packet Classifier Using a Parallel Branching Program MachineHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura. 745-752 [doi]
- A Computation and Power Reduction Technique for H.264 Intra PredictionYusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu. 753-760 [doi]
- Hardware-Based Speed Up of Face Recognition Towards Real-Time PerformanceI. Sajid, Sotirios G. Ziavras, M. M. Ahmed. 763-770 [doi]
- An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network EmulationBarend van Liempd, Daniel Herrera, Miguel Figueroa. 771-778 [doi]
- A Multicore Embedded Processor for Fingerprint RecognitionGiovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari. 779-784 [doi]
- H.264 Color Components Video Decoding Parallelization on Multi-core ProcessorsElias Baaklini, Hassan Sbeity, Smaïl Niar, Nouhad Amaneddine. 785-790 [doi]
- New Digital Control Technique for Improving Transient Response in DC - DC ConvertersMajd Ghazi Batarseh, Ehab Shobaki, Xiang Fang, Haibing Hu, Issa Batarseh. 793-796 [doi]
- A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential CircuitsMahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori. 797-800 [doi]
- A Multicore SDR Architecture for Reconfigurable WiMAX DownlinkPedro Suarez-Casal, Angel Carro-Lagoa, José Antonio García-Naya, Luis Castedo. 801-804 [doi]
- Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPGJiri Balcarek, Petr Fiser, Jan Schmidt. 805-808 [doi]
- Gracefully Degrading Circuit Controllers Based on PolytronicsRichard Ruzicka. 809-812 [doi]
- LEON3 ViP: A Virtual Platform with Fault Injection CapabilitiesAntonio da Silva, Sebastian Sanchez. 813-816 [doi]
- Reconfigurable Fault-Tolerant System SychronizationJan Balach, Ondrej Novák. 817-820 [doi]
- Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of KernelsYi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang. 823-830 [doi]