Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

Marcus Jeitler, Jakob Lechner. Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. In Sebastián López, editor, 13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France. pages 219-225, IEEE, 2010. [doi]

Abstract

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