Samy Meftali - researchr alias

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Viewing Publication 1 - 46 from 46

2024

A novel grey wolf optimization algorithm based on geometric transformations for gene selection and cancer classificationAli Dabba, Abdelkamel Tari, Samy Meftali. tjs, 80(4):4808-4840, March 2024. [doi]

2023

A new multi-objective binary Harris Hawks optimization for gene selection in microarray dataAli Dabba, Abdelkamel Tari, Samy Meftali. jaihc, 14(4):3157-3176, 2023. [doi]

2021

Gene selection and classification of microarray data method based on mutual information and moth flame algorithmAli Dabba, Abdelkamel Tari, Samy Meftali, Rabah Mokhtari. eswa, 166:114012, 2021. [doi]

Hybridization of Moth flame optimization algorithm and quantum computing for gene selection in microarray dataAli Dabba, Abdelkamel Tari, Samy Meftali. jaihc, 12(2):2731-2750, 2021. [doi]

2020

A survey on screenlogger attacks as well as countermeasuresHugo Sbai, Jassim Happa, Michael Goldsmith, Samy Meftali. ijes, 12(4):441-452, 2020. [doi]

Dataset Construction and Analysis of Screenshot MalwareHugo Sbaï, Jassim Happa, Michael Goldsmith, Samy Meftali. trustcom 2020: 646-655 [doi]

2019

An Optimal Allocation of Tracking Tasks in a SW/HW Fog/Cloud Based Distributed Video Surveillance SystemUgo Sbai, Samy Meftali, Djamel Aouali. jcm, 14(2):159-163, 2019. [doi]

2018

A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-ChipGilberto Ochoa-Ruiz, Pamela Wattebled, Maamar Touiza, Florent de Lamotte, El-Bay Bourennane, Samy Meftali, Jean-Luc Dekeyser, Jean-Philippe Diguet. jpdc, 112:1-19, 2018. [doi]

A Survey of Keylogger and Screenlogger Attacks in the Banking Sector and Countermeasures to ThemHugo Sbai, Michael Goldsmith, Samy Meftali, Jassim Happa. css 2018: 18-32 [doi]

2014

Model-driven design flow for distributed control in reconfigurable FPGA systemsChiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah, Jean-Luc Dekeyser. dasip 2014: 1-6 [doi]

2013

A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing schemeMajdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki. integration, 46(4):404-412, 2013. [doi]

Decentralized control for dynamically reconfigurable FPGA systemsChiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser. mam, 37(8-A):871-884, 2013. [doi]

2012

System level modeling methodology of NoC design from UML-MARTE to VHDLMajdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki. dafes, 16(4):161-187, 2012. [doi]

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACTGilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser. rsp 2012: 107-113 [doi]

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case studyGilberto Ochoa-Ruiz, O. Labbani-Narsis, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser. reconfig 2012: 1-8 [doi]

Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternativesImran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser. jsa, 58(5):178-194, 2012. [doi]

Semi-distributed Control for FPGA-based Reconfigurable SystemsChiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser. dsd 2012: 185-192 [doi]

Distributed control for reconfigurable FPGA systems: A high-level design approachChiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser. recosoc 2012: 1-8 [doi]

2011

2010

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory AnalysisSana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. dsd 2010: 706-713 [doi]

A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantizationMajdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki. isspit 2011: 528-531 [doi]

Vers la reconfiguration dynamique dans les systèmes embarqués: de la modélisation à l'implémentation. (Toward Dynamically Reconfigurable in Embedded Systems: From Models to Implementations)Samy Meftali. 2010. [doi]

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generationImran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Samy Meftali, Jean-Luc Dekeyser. ijes, 4(3/4):204-224, 2010. [doi]

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generationImran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. dasip 2010: 68-75 [doi]

2009

High level modeling of Dynamic Reconfigurable FPGAsImran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. ijrc, 2009, 2009. [doi]

2008

Using an MDE Approach for Modeling of Interconnection NetworksImran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser. ispan 2008: 289-294 [doi]

MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAsImran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. estimedia 2008: 47-52 [doi]

2007

An MPSoC Performance Estimation Framework Using Transaction Level ModelingRabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser. rtcsa 2007: 525-533 [doi]

Massively parallel processing on a chipPhilippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser. cf 2007: 277-286 [doi]

2006

Multilevel MPSoC Performance Evaluation Using MDE ApproachRabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser. issoc 2006: 1-4 [doi]

Estimating Energy Consumption for an MPSoC Architectural ExplorationRabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser. arcs 2006: 298-310 [doi]

2005

2004

2002

Automatic generation of embedded memory wrapper for multiprocessor SoCFerid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya. dac 2002: 596-601 [doi]

Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC DesignAhmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli. isss 2002: 26-31 [doi]

Exploration d'architectures et allocation/affectation mémoire dans les systèmes multiprocesseurs mono puce = Architectures exploration and memory allocation/assignment in multiprocessor SoC. (Architectures exploration and memory allocation/assignment in multiprocessor SoC)Samy Meftali. PhD thesis, Grenoble Institute of Technology, France, 2002. [doi]

2001

An optimal memory allocation for application-specific multiprocessor system-on-chipSamy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya. isss 2001: 19-24

Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared MemorySamy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya. ifip10-5 2002: 193-204

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