Table of Contents

• Wall street evaluates EDAMoshe Gavrielov, Richard Goering, Lucio Lanza, Vishal Saluja, Jay Vleeschhouwer. 1 [doi]
• IP delivery for FPGAs using Applets and JHDLMichael J. Wirthlin, Brian McMurtrey. 2-7 [doi]
• Watermarking integer linear programming solutionsSeapahn Megerian, Milenko Drinic, Miodrag Potkonjak. 8-13 [doi]
• Model design using hierarchical web-based librariesFabrice Bernardi, Jean François Santucci. 14-17 [doi]
• Behavioral synthesis via engineering changeMilenko Drinic, Darko Kirovski. 18-21 [doi]
• A universal technique for fast and flexible instruction-set architecture simulationAchim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann. 22-27 [doi]
• A fast on-chip profiler memoryRoman L. Lysecky, Susan Cotterell, Frank Vahid. 28-33 [doi]
• Design of an one-cycle decompression hardware for performance increase in embedded systemsHaris Lekatsas, Jörg Henkel, Venkata Jakkula. 34-39 [doi]
• A factorization-based framework for passivity-preserving model reduction of RLC systemsQ. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh. 40-45 [doi]
• Model order reduction for strictly passive and causal distributed systemsLuca Daniel, Joel R. Phillips. 46-51 [doi]
• Guaranteed passive balancing transformations for model order reductionJoel R. Phillips, Luca Daniel, Luis Miguel Silveira. 52-57 [doi]
• Uncertainty-aware circuit optimizationXiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski. 58-63 [doi]
• Congestion-driven codesign of power and signal networksHaihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif. 64-69 [doi]
• On metrics for comparing routability estimation methods for FPGAsPariVallal Kannan, Shankar Balachandran, Dinesh Bhatia. 70-75 [doi]
• Tools or users: which is the bigger bottleneck?Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven. 76-77 [doi]
• Life is CMOS: why chase the life after?George Sery, Shekhar Borkar, Vivek De. 78-83 [doi]
• The next chip challenge: effective methods for viable mixed technology SoCsH. Bernhard Pogge. 84-87 [doi]
• Few electron devices: towards hybrid CMOS-SET integrated circuitsAdrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier. 88-93 [doi]
• Carbon nanotube field-effect transistors and logic circuitsR. Martel, V. Derycke, J. Appenzeller, Shalom J. Wind, Ph. Avouris. 94-98 [doi]
• Efficient state representation for symbolic simulationValeria Bertacco, Kunle Olukotun. 99-104 [doi]
• Handling special constructs in symbolic simulationAlfred Kölbl, James H. Kukula, Kurt Antreich, Robert F. Damiano. 105-110 [doi]
• A hybrid verification approach: getting deep into the designScott Hazelhurst, Osnat Weissberg, Gila Kamhi, Limor Fix. 111-116 [doi]
• Can BDDs compete with SAT solvers on bounded model checking?Gianpiero Cabodi, Paolo Camurati, Stefano Quer. 117-122 [doi]
• RTL c-based methodology for designing and verifying a multi-threaded processorLuc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng. 123-128 [doi]
• High-Level specification and automatic generation of IP interface monitorsMarcio T. Oliveira, Alan J. Hu. 129-134 [doi]
• Achieving maximum performance: a method for the verification of interlocked pipeline control logicKerstin Eder, Geoff Barrett. 135-140 [doi]
• Formal verification of module interfaces against real time specificationsArindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee. 141-145 [doi]
• Automated timing model generationAjay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu. 146-151 [doi]
• Timing model extraction of hierarchical blocks by graph reductionCho W. Moon, Harish Kriplani, Krishna P. Belkhale. 152-157 [doi]
• Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparencyMartin Foltin, Brian Foutz, Sean Tyler. 158-163 [doi]
• An implication-based method to detect multi-cycle paths in large sequential circuitsHiroyuki Higuchi. 164-169 [doi]
• The wearable motherboard: a framework for personalized mobile information processing (PMIP)Sungmee Park, Kenneth Mackenzie, Sundaresan Jayaraman. 170-174 [doi]
• Challenges and opportunities in electronic textiles modeling and optimizationDiana Marculescu, Radu Marculescu, Pradeep K. Khosla. 175-180 [doi]
• Analog intellectual property: now? Or never?Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore. 181-182 [doi]
• Task scheduling and voltage selection for energy minimizationYumin Zhang, Xiaobo Hu, Danny Z. Chen. 183-188 [doi]
• Battery-conscious task sequencing for portable devices including voltage/clock scalingDaler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti. 189-194 [doi]
• An energy saving strategy based on adaptive loop parallelizationIsmail Kadayif, Mahmut T. Kandemir, Mustafa Karaköy. 195-200 [doi]
• River PLAs: a regular circuit structureFan Mo, Robert K. Brayton. 201-206 [doi]
• Layout-aware synthesis of arithmetic circuitsJunhyung Um, Taewhan Kim. 207-212 [doi]
• Automatic data migration for reducing energy consumption in multi-bank memory systemsVictor De La Luz, Mahmut T. Kandemir, Ibrahim Kolcu. 213-218 [doi]
• Exploiting shared scratch pad memory space in embedded multiprocessor systemsMahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary. 219-224 [doi]
• Address assignment combined with scheduling in DSP code generationYoonseo Choi, Taewhan Kim. 225-230 [doi]
• Multifunctional photonic integration for the agile optical internetEdward H. Sargent. 231-234 [doi]
• Computer aided design of long-haul optical transmission systemsJames G. Maloney, Brian E. Brewington, Curtis R. Menyuk. 235 [doi]
• A fast optical propagation technique for modeling micro-optical systemsTimothy P. Kurzweg, Steven P. Levitan, Jose A. Martinez, Mark Kahrs, Donald M. Chiarulli. 236-241 [doi]
• Nanometer design: what hurts next...?Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi. 242 [doi]
• Low-cost sequential ATPG with clock-control DFTMiron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick. 243-248 [doi]
• Effective diagnostics through interval unloads in a BIST environmentPeter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston. 249-254 [doi]
• On output response compression in the presence of unknown output valuesIrith Pomeranz, Sandip Kundu, Sudhakar M. Reddy. 255-258 [doi]
• Software-based diagnosis for processorsLi Chen, Sujit Dey. 259-262 [doi]
• Design of a high-throughput low-power IS95 Viterbi decoderXun Liu, Marios C. Papaefthymiou. 263-268 [doi]
• A detailed cost model for concurrent use with hardware/software co-designDaniel Ragan, Peter Sandborn, Paul Stoaks. 269-274 [doi]
• Efficient code synthesis from extended dataflow graphs for multimedia applicationsHyunok Oh, Soonhoi Ha. 275-280 [doi]
• Transformation based communication and clock domain refinement for system designIngo Sander, Axel Jantsch. 281-286 [doi]
• Model composition for scheduling analysis in platform designKai Richter, Dirk Ziegenbein, Marek Jersak, Rolf Ernst. 287-292 [doi]
• Timed compiled-code simulation of embedded software for performance analysis of SOC designJong-Yeol Lee, In-Cheol Park. 293-298 [doi]
• Automated equivalence checking of switch level circuits Simon Jolly, Atanas N. Parashkevov, Tim McDougall. 299-304 [doi]
• A practical and efficient method for compare-point matchingDemos Anastasakis, Robert F. Damiano, Hi-Keung Tony Ma, Ted Stanion. 305-310 [doi]
• Self-referential verification of gate-level implementations of arithmetic circuitsYing-Tsai Chang, Kwang-Ting Cheng. 311-316 [doi]
• Whither (or wither?) ASIC handoff?Michael Santarini, Sudhakar Jilla, Mark Miller, Tommy Eng, Sandeep Khanna, Kamalesh N. Ruparel, Tom Russell, Kazu Yamada. 317-318 [doi]
• Software synthesis from synchronous specifications using logic simulation techniquesYunjian Jiang, Robert K. Brayton. 319-324 [doi]
• Complex library mapping for embedded software using symbolic algebraArmita Peymandoust, Giovanni De Micheli, Tajana Simunic. 325-330 [doi]
• Retargetable binary utilitiesMaghsoud Abbaspour, Jianwen Zhu. 331-336 [doi]
• Exploiting operation level parallelism through dynamically reconfigurable datapathsZhining Huang, Sharad Malik. 337-342 [doi]
• Dynamic hardware plugins in an FPGA with partial run-time reconfigurationEdson L. Horta, John W. Lockwood, David E. Taylor, David Parlour. 343-348 [doi]
• A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulatorJinghuan Chen, Jaekyun Moon, Kia Bazargan. 349-354 [doi]
• Embedded software-based self-testing for SoC designAngela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey. 355-360 [doi]
• A novel wavelet transform based transient current analysis for fault detection and localizationSwarup Bhunia, Kaushik Roy, Jaume Segura. 361-366 [doi]
• Signal integrity fault analysis using reduced-order modelingAmir Attarha, Mehrdad Nourani. 367-370 [doi]
• Enhancing test efficiency for delay fault testing using multiple-clocked schemesJing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams. 371-374 [doi]
• Going mobile: the next horizon for multi-million gate designs in the semi-conductor industryChristian Berthet. 375-378 [doi]
• HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power deliveryYahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen. 379-384 [doi]
• High-level current macro-model for power-grid analysisSrinivas Bodapati, Farid N. Najm. 385-390 [doi]
• Macro-modeling concepts for the chip electrical interfaceBrian W. Amick, Claude R. Gauthier, Dean Liu. 391-394 [doi]
• Modeling and analysis of regular symmetrically structured power/ground distribution networksHui Zheng, Lawrence T. Pileggi. 395-398 [doi]
• Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transientsMustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen. 399-404 [doi]
• Resynthesis and peephole transformations for the optimization of large-scale asynchronous systemsTiberiu Chelcea, Steven M. Nowick. 405-410 [doi]
• Design of asynchronous circuits by synchronous CAD toolsAlex Kondratyev, Kelvin Lwin. 411-414 [doi]
• Implementing asynchronous circuits using a conventional EDA tool-flowChristos P. Sotiriou. 415-418 [doi]
• Transformation rules for designing CNOT-based quantum circuitsKazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita. 419-424 [doi]
• Fast three-level logic minimization based on autosymmetryAnna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli. 425-430 [doi]
• An efficient optimization--based technique to generate posynomial performance models for analog integrated circuitsWalter Daems, Georges G. E. Gielen, Willy M. C. Sansen. 431-436 [doi]
• Remembrance of circuits past: macromodeling by data mining in large analog design spacesHongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley. 437-442 [doi]
• Optimal design of delta-sigma ADCs by design space explorationOvidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen. 443-448 [doi]
• Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converterJan Vandenbussche, K. Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen. 449-454 [doi]
• Petri net modeling of gate and interconnect delays for power estimationAshok K. Murugavel, N. Ranganathan. 455-460 [doi]
• Power estimation in global interconnects and its reduction using a novel repeater optimization methodologyPawan Kapur, Gaurav Chandra, Krishna Saraswat. 461-466 [doi]
• Low-swing clock domino logic incorporating dual supply and dual threshold voltagesSeong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang. 467-472 [doi]
• DRG-cache: a data retention gated-ground cache for low powerAmit Agarwal, Hai Li, Kaushik Roy. 473-478 [doi]
• Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant?Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey. 479 [doi]
• Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering techniqueMohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi. 480-485 [doi]
• Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessorsTanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar. 486-491 [doi]
• An optimal voltage synthesis technique for a power-efficient satellite applicationDong-In Kang, Jinwoo Suh, Stephen P. Crago. 492-497 [doi]
• Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuitsMichael H. Perrott. 498-503 [doi]
• Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev methodBaolin Yang, Joel R. Phillips. 504-509 [doi]
• A time-domain RF steady-state method for closely spaced tonesJaijeet S. Roychowdhury. 510-513 [doi]
• An algorithm for frequency-domain noise analysis in nonlinear systemsGiorgio Casinovi. 514-517 [doi]
• System-level performance optimization of the data queueing memory management in high-speed network processorsChantal Ykman-Couvreur, J. Lambrecht, Diederik Verkest, Francky Catthoor, Aristides Nikologiannis, George E. Konstantoulakis. 518-523 [doi]
• Analysis of power consumption on switch fabrics in network routersTerry Tao Ye, Giovanni De Micheli, Luca Benini. 524-529 [doi]
• Memory optimization in single chip network switch fabricsDavid Whelihan, Herman Schmit. 530-535 [doi]
• Behavioral modeling of (coupled) harmonic oscillatorsPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. 536-541 [doi]
• Model checking algorithms for analog verificationWalter Hartong, Lars Hedrich, Erich Barke. 542-547 [doi]
• Regularization of hierarchical VHDL-AMS models using bipartite graphsJochen Mades, Manfred Glesner. 548-551 [doi]
• Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materialsYehia Massoud, Jacob White. 552-555 [doi]
• A general probabilistic framework for worst case timing analysisMichael Orshansky, Kurt Keutzer. 556-561 [doi]
• False timing path identification using ATPG techniques and delay-based informationJing Zeng, Magdy S. Abadir, Jacob A. Abraham. 562-565 [doi]
• False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validationJing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng. 566-569 [doi]
• A fast, inexpensive and scalable hardware acceleration technique for functional simulationSrihari Cadambi, Chandra Mulpuri, Pranav Ashar. 570-575 [doi]
• Formal verification methods: getting around the brick wallDavid L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan, Gunnar Stålmarck, Curt Widdoes. 576-577 [doi]
• S-Tree: a technique for buffered routing tree synthesisMilos Hrkic, John Lillis. 578-583 [doi]
• An algorithm for integrated pin assignment and buffer planningHua Xiang, D. F. Wong, Xiaoping Tang. 584-589 [doi]
• An efficient routing databaseNarendra V. Shenoy, William Nicholls. 590-595 [doi]
• Automatic generation of embedded memory wrapper for multiprocessor SoCFerid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya. 596-601 [doi]
• A novel synthesis technique for communication controller hardware from declarative data communication protocol specificationsRobert Siegmund, Dietmar Müller. 602-607 [doi]
• An integrated algorithm for memory allocation and assignment in high-level synthesisJaewon Seo, Taewhan Kim, Preeti Ranjan Panda. 608-611 [doi]
• High-level synthesis of multiple-precision circuitsindependent of data-objects lengthMaría C. Molina, José M. Mendías, Román Hermida. 612-615 [doi]
• Schedulability of event-driven code blocks in real-time embedded systemsSamarjit Chakraborty, Thomas Erlebach, Simon Künzli, Lothar Thiele. 616-621 [doi]
• Associative caches in formal software timing analysisFabian Wolf, Jan Staschulat, Rolf Ernst. 622-627 [doi]
• Compiler-directed scratch pad memory hierarchy design and managementMahmut T. Kandemir, Alok N. Choudhary. 628-633 [doi]
• Unlocking the design secrets of a 2.29 Gb/s Rijndael processorPatrick Schaumont, Henry Kuo, Ingrid Verbauwhede. 634-639 [doi]
• The iCOREtm 520 MHz synthesizable CPU coreNick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis. 640-645 [doi]
• A flexible accelerator for layer 7 networking applicationsGokhan Memik, William H. Mangione-Smith. 646-651 [doi]
• What s the next EDA driver?Jan M. Rabaey, Joachim Kunkel, Dennis Brophy, Raul Camposano, Davoud Samani, Larry Lerner, Rick Hetherington. 652 [doi]
• Estimation of the likelihood of capacitive coupling noiseSarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul. 653-658 [doi]
• Crosstalk noise estimation for noise managementPaul B. Morton, Wayne Wei-Ming Dai. 659-664 [doi]
• Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmaxByron Krauter, David Widiger. 665-668 [doi]
• Towards global routing with RLC crosstalk constraintsJames D. Z. Ma, Lei He. 669-672 [doi]
• Reduction of SOC test data volume, scan power and testing time using alternating run-length codesAnshuman Chandra, Krishnendu Chakrabarty. 673-678 [doi]
• Embedded test control schemes for compression in SOCsDouglas Kay, Sung Chung, Samiha Mourad. 679-684 [doi]
• Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCsVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. 685-690 [doi]
• Communication architecture based power management for battery efficient system designKanishka Lahiri, Sujit Dey, Anand Raghunathan. 691-696 [doi]
• Scheduler-based DRAM energy managementVictor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. 697-702 [doi]
• An integer linear programming based approach for parallelizing applications in On-chip multiprocessorsIsmail Kadayif, Mahmut T. Kandemir, Ugur Sezer. 703-708 [doi]
• Embedding infrastructure IP for SOC yield improvementYervant Zorian. 709-712 [doi]
• Using embedded FPGAs for SoC yield improvementMiron Abramovici, Charles E. Stroud, Marty Emmert. 713-724 [doi]
• A proof engine approach to solving combinational design automation problemsGunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna. 725-730 [doi]
• Solving difficult SAT instances in the presence of symmetryFadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah. 731-736 [doi]
• Satometer: how much have we searched?Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah. 737-742 [doi]
• SAT with partial clauses and back-leapsSlawomir Pilarski, Gracia Hu. 743-746 [doi]
• Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solverMalay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik. 747-750 [doi]
• A solenoidal basis method for efficient inductance extractionHemant Mahawar, Vivek Sarin, Weiping Shi. 751-756 [doi]
• On the efficacy of simplified 2D on-chip inductance modelsTao Lin, Michael W. Beattie, Lawrence T. Pileggi. 757-762 [doi]
• A physical model for the transient response of capacitively loaded distributed rlc interconnectsRaguraman Venkatesan, Jeffrey A. Davis, James D. Meindl. 763-766 [doi]
• HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOCAdil Koukab, Catherine Dehollain, Michel J. Declercq. 767-770 [doi]
• Combined BEM/FEM substrate resistance modelingEelco Schrik, N. P. van der Meijs. 771-776 [doi]
• System design methodologies for a wireless security processing platformSrivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass. 777-782 [doi]
• Constraint-driven communication synthesisAlessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 783-788 [doi]
• Component-based design approach for multicore SoCsWander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava. 789-794 [doi]
• Traffic analysis for on-chip networks design of multimedia applicationsGirish Varatkar, Radu Marculescu. 795-800 [doi]
• Deriving a simulation input generator and a coverage metric from a formal specificationKanna Shimizu, David L. Dill. 801-806 [doi]
• Hole analysis for functional coverage dataOded Lachish, Eitan Marcus, Shmuel Ur, Avi Ziv. 807-812 [doi]
• Effective safety property checking using simulation-based sequential ATPGShuo Sheng, Koichiro Takayama, Michael S. Hsiao. 813-818 [doi]
• A comparison of three verification techniques: directed testing, pseudo-random testing and property checkingMike Bartley, Darren Galpin, Tim Blackmore. 819-823 [doi]
• Energy-efficient communication protocolsCarla-Fabiana Chiasserini, Pavan Nuggehalli, Vikram Srinivasan. 824-829 [doi]
• Reliable and energy-efficient digital signal processingNaresh R. Shanbhag. 830-835 [doi]
• CMOS: a paradigm for low power wireless?Michiel Steyaert, Peter J. Vancorenland. 836-841 [doi]
• TCG-S: orthogonal coupling of P:::*:::-admissible representations for general floorplansJai-Ming Lin, Yao-Wen Chang. 842-847 [doi]
• Floorplanning with alignment and performance constraintsXiaoping Tang, D. F. Wong. 848-853 [doi]
• Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion controlKe Zhong, Shantanu Dutt. 854-859 [doi]
• Coping with buffer delay change due to power and ground noiseLauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer. 860-865 [doi]
• Osculating Thevenin model for predicting delay and slew of capacitively characterized cellsBernard N. Sheehan. 866-869 [doi]
• Timed pattern generation for noise-on-delay calculationSeung Hoon Choi, Kaushik Roy, Florentin Dartu. 870-873 [doi]
• VeriCDF: a new verification methodology for charged device failuresJaesik Lee, Ki-Wook Kim, Sung-Mo Kang. 874-879 [doi]
• A framework for evaluating design tradeoffs in packet processing architecturesLothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli. 880-885 [doi]
• Energy estimation and optimization of embedded VLIW processors based on instruction clusteringAndrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon. 886-891 [doi]
• Energy exploration and reduction of SDRAM memory systemsYongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Gyu Lee, Kwanho Kim, Naehyuck Chang. 892-897 [doi]
• Coordinated transformations for high-level synthesis of high performance microprocessor blocksSumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem. 898-903 [doi]
• Forward-looking objective functions: concept & applications in high level synthesisJennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak. 904-909 [doi]
• ILP-based engineering changeFarinaz Koushanfar, Jennifer L. Wong, Jessica Feng, Miodrag Potkonjak. 910-915 [doi]