Renu Mehra - researchr alias

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Viewing Publication 1 - 11 from 11

2015

Message from the general chairsLuca Benini, Renu Mehra, Mauro Olivieri. islped 2015: 1-2 [doi]

2012

Industry focus session on low-power designClive Bittlestone, Jim Kardach, Renu Mehra, David Flynn, Barry M. Pangrle. islped 2012: 63-64 [doi]

Commercial low-power EDA tools: a reviewRenu Mehra. islped 2012: 67-72 [doi]

2002

RTL c-based methodology for designing and verifying a multi-threaded processorLuc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng. dac 2002: 123-128 [doi]

2000

Automating RT-Level Operand Isolation to Minimize Power Consumption in DatapathsMichael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch. date 2000: 624 [doi]

1997

A partitioning scheme for optimizing interconnect powerRenu Mehra, Lisa M. Guerra, Jan M. Rabaey. jssc, 32(3):433-443, 1997. [doi]

1996

An Integrated CAD Environment for Low-Power DesignPaul E. Landman, Renu Mehra, Jan M. Rabaey. dt, 13(2):72-82, 1996. [doi]

Exploiting regularity for low-power designRenu Mehra, Jan M. Rabaey. iccad 1996: 166-172 [doi]

Low-power architectural synthesis and the impact of exploiting localityRenu Mehra, Lisa M. Guerra, Jan M. Rabaey. vlsisp, 13(2-3):239-258, 1996. [doi]

1995

Optimizing power using transformationsAnantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen. tcad, 14(1):12-31, 1995. [doi]

Design guidance in the power dimensionJan M. Rabaey, Lisa M. Guerra, Renu Mehra. icassp 1995: 2837-2840 [doi]

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