Table of Contents

• Energy-secure computingPradip Bose. 1-2 [doi]
• Write-optimized reliable design of STT MRAMYusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy. 3-8 [doi]
• High-performance low-energy STT MRAM based on balanced write schemeDongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy. 9-14 [doi]
• Design benchmarking to 7nm with FinFET predictive technology modelsSaurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao. 15-20 [doi]
• TSV array utilization in low-power 3D clock network designXin Zhao, Sung Kyu Lim. 21-26 [doi]
• Practically scalable floorplanning with voltage island generationSong Chen, Xiaolin Zhang, Takeshi Yoshimura. 27-32 [doi]
• Thermal-aware sampling in architectural simulationEhsan K. Ardestani, Elnaz Ebrahimi, Gabriel Southern, Jose Renau. 33-38 [doi]
• ER: elastic RESET for low power and long endurance MLC based phase change memoryLei Jiang, Youtao Zhang, Jun Yang 0002. 39-44 [doi]
• A dual-mode architecture for fast-switching STT-RAMZhenyu Sun, Hai Li, Wenqing Wu. 45-50 [doi]
• ASCIB: adaptive selection of cache indexing bits for removing conflict missesAlberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García. 51-56 [doi]
• Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systemsJieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai. 57-62 [doi]
• Industry focus session on low-power designClive Bittlestone, Jim Kardach, Renu Mehra, David Flynn, Barry M. Pangrle. 63-64 [doi]
• Advances in ultrabook™ platform power managementJim Kardach. 65-66 [doi]
• Commercial low-power EDA tools: a reviewRenu Mehra. 67-72 [doi]
• An ARM perspective on addressing low-power energy-efficient SoC designsDavid Flynn. 73-78 [doi]
• A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assistYi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang. 79-84 [doi]
• A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) schemeShusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. 85-90 [doi]
• An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMsDaeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester. 91-96 [doi]
• Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessorsDa-Cheng Juan, Diana Marculescu. 97-102 [doi]
• Power conversion efficiency characterization and optimization for smartphonesWoojoo Lee, Yanzhi Wang, Donghwa Shin, Naehyuck Chang, Massoud Pedram. 103-108 [doi]
• Dynamic reconfiguration of photovoltaic energy harvesting system in hybrid electric vehiclesYanzhi Wang, Xue Lin, Naehyuck Chang, Massoud Pedram. 109-114 [doi]
• Battery management for grid-connected PV systems with a batterySangyoung Park, Yanzhi Wang, Younghyun Kim, Naehyuck Chang, Massoud Pedram. 115-120 [doi]
• Panel: going green across communications and storage systems: control of power in non-mobile devicesKenneth Wagner, Martin St. Laurent, Robert C. Aitken, Hugh Barrass, Randall Robinson. 121-122 [doi]
• Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systemsElif S. Mungan, Chao Lu, Vijay Raghunathan, Kaushik Roy. 123-128 [doi]
• Static low power verification at transistor level for SoC designJérôme Lescot, Vincent Bligny, Dina Medhat, Didier Chollat-Namy, Ziyang Lu, Sophie Billy, Mark Hofmann. 129-134 [doi]
• CCP: common case promotion for improved timing error resilience with energy efficiencyLu Wan, Deming Chen. 135-140 [doi]
• Energy-optimal caches with guaranteed lifetimeMirko Loghi, Haroon Mahmood, Andrea Calimera, Massimo Poncino, Enrico Macii. 141-146 [doi]
• Spin as state variable for computation: prospects and perspectivesKaushik Roy. 147-148 [doi]
• Register file write data gating techniques and break-even analysis modelEric Donkoh, Teck Siong Ong, Yan Nee Too, Patrick Chiang. 149-154 [doi]
• A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalabilityEric Donkoh, Patrick Chiang. 155-160 [doi]
• T design methodology for ultra low voltage operationsMingoo Seok. 161-166 [doi]
• A programmable resistive power grid for post-fabrication flexibility and energy tradeoffsKyle Craig, Yousef Shakhsheer, Sudhanshu Khanna, Saad Arrabi, John Lach, Benton H. Calhoun, Stephen Kosonocky. 167-172 [doi]
• Improving energy efficiency of write-asymmetric memories by log style writeGuangyu Sun, Yaojun Zhang, Yu Wang 0002, Yiran Chen. 173-178 [doi]
• Process variation aware data management for STT-RAM cache designZhenyu Sun, Xiuyuan Bi, Hai Li. 179-184 [doi]
• TapeCache: a high density, energy efficient cache based on domain wall memoryRangharajan Venkatesan, Vivek J. Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan. 185-190 [doi]
• A software approach for combating asymmetries of non-volatile memoriesYong Li 0009, Yiran Chen, Alex K. Jones. 191-196 [doi]
• Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retentionYuhao Wang, Chun Zhang, Hao Yu, Wei Zhang. 197-202 [doi]
• TAP: token-based adaptive power gatingAndrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong. 203-208 [doi]
• Design trade-offs for high density cross-point resistive memoryDimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie. 209-214 [doi]
• Performance and energy-efficiency improvement through modified CPL in organic transistor integrated circuitsMingoo Seok. 215-220 [doi]
• Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operationKyle Craig, Yousef Shakhsheer, Benton H. Calhoun. 221-224 [doi]
• BiN: a buffer-in-NUCA scheme for accelerator-rich CMPsJason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman. 225-230 [doi]
• Adopting TLB index-based tagging to data caches for tag energy reductionJongmin Lee 0002, Soontae Kim. 231-236 [doi]
• Static and dynamic co-optimizations for blocks mapping in hybrid cachesYu-Ting Chen, Jason Cong, Hui Huang 0001, Chunyue Liu, Raghu Prabhakar, Glenn Reinman. 237-242 [doi]
• Design space exploration of workload-specific last-level cachesKarthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir. 243-248 [doi]
• Low-power adaptive RF system design using real-time fuzzy noise-distortion controlDebashis Banerjee, Shreyas Sen, Aritra Banerjee, Abhijit Chatterjee. 249-254 [doi]
• Designing for dark silicon: a methodological perspective on energy efficient systemsJason Allred, Sanghamitra Roy, Koushik Chakraborty. 255-260 [doi]
• HANDS: heterogeneous architectures and networks-on-chip design and simulationDavide Zoni, Simone Corbetta, William Fornaciari. 261-266 [doi]
• XIOSim: power-performance modeling of mobile x86 coresSvilen Kanev, Gu-Yeon Wei, David Brooks. 267-272 [doi]
• LogStore: toward energy-proportional storage serversWei Zheng, Ana Paula Centeno, Frederic T. Chong, Ricardo Bianchini. 273-278 [doi]
• A game theoretic resource allocation for overall energy minimization in mobile cloud computing systemYang Ge, Yukan Zhang, Qinru Qiu, Yung-Hsiang Lu. 279-284 [doi]
• A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmabilityHimanshu Markandeya, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy. 285-290 [doi]
• Understanding the impact of laptop power saving options on user satisfaction using physiological sensorsMatthew Schuchhardt, Benjamin Scholbrock, Utku Pamuksuz, Gokhan Memik, Peter A. Dinda, Robert P. Dick. 291-296 [doi]
• MultiScale: memory system DVFS with multiple memory controllersQingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini. 297-302 [doi]
• Semantics-driven sensor configuration for energy reduction in medical sensor networksJames Bradley Wendt, Saro Meguerdichian, Hyduke Noshadi, Miodrag Potkonjak. 303-308 [doi]
• Voltage droop reduction for multiple-power domain SoCs with on-die LDO using output voltage boost and adaptive response scalingTetsutaro Hashimoto, Satoshi Tanabe, Kouichi Nakayama, Hisanori Fujisawa. 309-314 [doi]
• A 33μW 42 GOPS/W 64x64 pixel vision sensor with dynamic background subtraction for scene interpretationNicola Cottini, Massimo Gottardi, Nicola Massari, Roberto Passerone, Zeev Smilansky. 315-320 [doi]
• m-C filter for multichannel neuro-potential signal conditioningAnvesha Amaravati, Maryam Shojaei Baghini. 321-326 [doi]
• A charge pump based receiver circuit for voltage scaled interconnectAatmesh Shrivastava, John Lach, Bemton Calhoun. 327-332 [doi]
• 0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOSAkira Saito, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya. 333-338 [doi]
• A study of the effectiveness of CPU consolidation in a virtualized multi-core server systemInkwon Hwang, Timothy Kam, Massoud Pedram. 339-344 [doi]
• Energy-efficient scheduling on heterogeneous multi-core architecturesJason Cong, Bo Yuan. 345-350 [doi]
• MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systemsQing'an Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yanxiang He. 351-356 [doi]
• Energy-efficient signal processing in wearable embedded systems: an optimal feature selection approachHassan Ghasemzadeh, Navid Amini, Majid Sarrafzadeh. 357-362 [doi]
• Advanced power and thermal management for low-power, high-performance smartphonesHwisung Jung. 363-364 [doi]
• Ultra-low power challenges for the next generation ASICUming Ko. 365-366 [doi]
• The core-C6 (CC6) sleep state of the AMD bobcat x86 microprocessorAaron Rogers, David Kaplan, Eric Quinnell, Bill Kwan. 367-372 [doi]
• Evaluation of voltage stacking for near-threshold multicore computingSae Kyu Lee, David Brooks, Gu-Yeon Wei. 373-378 [doi]
• CHARM: a composable heterogeneous accelerator-rich microprocessorJason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman. 379-384 [doi]
• Something old and something new: P-states can borrow microarchitecture techniques tooYasuko Eckert, Srilatha Manne, Michael J. Schulte, David A. Wood. 385-390 [doi]
• Reducing L1 caches power by exploiting software semanticsZhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi Iyer, Tong Li 0003, Seung Eun Lee. 391-396 [doi]
• DRAM power-aware rank schedulingSukki Kim, Soontae Kim, Yebin Lee. 397-402 [doi]
• Energy-efficient GPU design with reconfigurable in-package graphics memoryJishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie. 403-408 [doi]
• Fan-speed-aware scheduling of data intensive jobsChristine S. Chan, Yanqin Jin, Yen-Kuan Wu, Kenny C. Gross, Kalyan Vaidyanathan, Tajana Simunic Rosing. 409-414 [doi]
• Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clustersAbbas Rahimi, Luca Benini, Rajesh Gupta. 415-420 [doi]