Geng-Cing Lin - researchr alias

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Viewing Publication 1 - 6 from 6

2012

An all-digital bit transistor characterization scheme for CMOS 6T SRAM arrayGeng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu. iscas 2012: 2485-2488 [doi]

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM arrayYi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih. vlsi-dat 2012: 1-4 [doi]

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assistYi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang. islped 2012: 79-84 [doi]

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAMShao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu. apccas 2012: 116-119 [doi]

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleederHao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu. iscas 2012: 1831-1834 [doi]

2011

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