Table of Contents

• Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than mooreKrishnendu Chakrabarty. 5 [doi]
• Recent research and emerging challenges in the System-Level Design of digital microfluidic biochipsPaul Pop, Elena Maftei, Jan Madsen. 6-11 [doi]
• Recent research and emerging challenges in design and optimization for digital microfluidic biochipsTsung-Wei Huang, Yan-You Lin, Jia-Wen Chang, Tsung-Yi Ho. 12-17 [doi]
• Tutorial: "Post silicon debug of SOC designs"Virendra Singh, Masahiro Fujita. 18 [doi]
• An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regionsWei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang. 19-23 [doi]
• A gate sizing method for glitch power reductionLei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz. 24-29 [doi]
• Novel adaptive keeper LBL technique for low power and high performance register filesNa Gong, Geng Tang, Jinhui Wang, Ramalingam Sridhar. 30-35 [doi]
• Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control systemXiaoyan Jia, Gerhard Fettweis. 36-41 [doi]
• A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuitYi-Ming Wang, Jen-Tsung Yu, Yuandi Surya, Chung-Hsun Huang. 42-47 [doi]
• A low-power all-digital phase modulator pair for LINC transmittersPing-Yuan Tsai, Tsan-Wen Chen, Chen-Yi Lee. 48-51 [doi]
• A low power wide tuning range VCO with coupled LC tanksShouxian Mou, Kaixue Ma, Kiat Seng Yeo, Nagarajan Mahalingam, Bharatha Kumar Thangarasu. 52-56 [doi]
• A design strategy for sub-threshold circuits considering energy-minimization and yield-maximizationJunya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato. 57-62 [doi]
• A silicon core for an acoustic archival tagGodi Fischer, H. Thomas Rossby. 63-69 [doi]
• A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variationsPo-Yu Kuo, Siwat Saibua, Dian Zhou. 70-75 [doi]
• Low power 120 KSPS 12bit SAR ADC with a novel switch control method for internal CDACAbhisek Dey, Tarun Kanti Bhattacharyya. 76-80 [doi]
• Simultaneous escape routing based on routability-driven net orderingJin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen. 81-86 [doi]
• A CAD methodology for automatic topology selection & sizingSupriyo Maji, Pradip Mandal. 87-92 [doi]
• System power analysis with DVFS on ESL virtual platformWen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen. 93-98 [doi]
• A 65nm standard cell set and flow dedicated to automated asynchronous circuits designMatheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans. 99-104 [doi]
• Double-differential recording and AGC using amplifier ASICShin-Liang Deng, Chun-Yi Li, Robert Rieger. 105-108 [doi]
• th order CT sigma delta for digital hearing aidsSyed R. Naqvi, Ilker Deligoz, Sayfe Kiaei, Bertan Bakkaloglu. 109-113 [doi]
• A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications systemHarry Tai, Peter Noel, Tad A. Kwasniewski. 114-117 [doi]
• Feasibility study for communication over Power Distribution Networks of microprocessorsRajesh Thirugnanam, Dong Sam Ha. 118-121 [doi]
• On-demand memory sub-system for multi-core SoCsPo-Tsang Huang, Yung Chang, Wei Hwang. 122-127 [doi]
• Well tapping methodologies in power-gating designKaijian Shi, David Tester. 128-131 [doi]
• Power-aware design technique for PAC Duo based embedded systemShui-An Wen, Huang-Lun Lin, Chi Wu, Chun-Chin Chen, Kun-Hsien Tsai, Wei-Min Cheng. 132-135 [doi]
• Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAMJanna Mezhibovsky, Adam Teman, Alexander Fish. 136-141 [doi]
• Ultra low power QC-LDPC decoder with high parallelismYing Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto. 142-145 [doi]
• A SAR ADC BIST for simplified linearity testAn-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting. 146-149 [doi]
• Concept and design of exhaustive-parallel search algorithm for Network-on-ChipMeganathan Deivasigamani, Shaghayeghsadat Tabatabaei, Naveed Mustafa, Hamza Ijaz, Haris Bin Aslam, Shaoteng Liu, Axel Jantsch. 150-155 [doi]
• TSV sharing through multiplexing for TSV count minimization in high-level synthesisWen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang. 156-159 [doi]
• Power characteristics of Asynchronous Networks-on-ChipMaher Rashed, Mohamed A. Abd El ghany, Mohammed Ismail. 160-165 [doi]
• Design of complex circuits using the Via-Configurable transistor array regular layout fabricMarc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González. 166-169 [doi]
• Yield-award placement optimization for Switched-Capacitor analog integrated circuitsChien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey. 170-173 [doi]
• An analytical model to estimate PCM failure probability due to process variationsMu-Tien Chang, Bruce Jacob. 174-177 [doi]
• Plenary: Boosting performance efficiency in multiprocessor systems through multi-threadingGideon D. Intrater. 178 [doi]
• Configurable workload generators for multicore architecturesAmayika Panda, Annie Avakian, Ranga Vemuri. 179-184 [doi]
• Computation and communication aware run-time mapping for NoC-based MPSoC platformsSamarth Kaushik, Amit Kumar Singh, Thambipillai Srikanthan. 185-190 [doi]
• De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chipsAzeez Sanusi, Magdy A. Bayoumi. 191-196 [doi]
• A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS controlHao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu. 197-200 [doi]
• Functional verifications for SoC software/hardware co-design: From virtual platform to physical platformYi-Li Lin, Alvin W. Y. Su. 201-206 [doi]
• CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessorsLiucheng Guo, Jiangfang Yi, Liang Zhang, Xiaoyin Wang, Dong Tong. 207-212 [doi]
• High reliability built-in self-detection and self-correction design for DCT/IDCT applicationChang-Hsin Cheng, Chun-Lung Hsu, Chung-Kai Liu, Shih-Yin Lin. 213-218 [doi]
• A register-transfer level testability analyzerYen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin. 219-224 [doi]
• Monitor strategies for variability reduction considering correlation between power and timing variabilityJoan Mauricio, Francesc Moll, Josep Altet. 225-230 [doi]
• A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flowRami F. Salem, Ahmed Arafa, Sherif Hany, Abdelrahman ElMously, Haitham Eissa, Mohamed Dessouky, David Nairn, Mohab H. Anis. 231-236 [doi]
• A 144-configuration context MEMS optically reconfigurable gate arrayYuichiro Yamaji, Minoru Watanabe. 237-241 [doi]
• VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codesMing-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang. 242-246 [doi]
• Low power Gm-boosted differential Colpitts VCOYi-Pei Su, Wei-Yi Hu, Jia-Wei Lin, Yun-Chung Chen, Sakir Sezer, Sao-Jie Chen. 247-250 [doi]
• A multi-segment clocking scheme to reduce on-chip EMIBehzad Mesgarzadeh, Iman Esmaeil Zadeh, Atila Alvandpour. 251-255 [doi]
• Luncheon Speaker: "Introduction to SoC testing"Laung-Terng Wang. 256-257 [doi]
• Baseband signal processing in SDRTzi-Dar Chiueh. 258 [doi]
• Software defined radio based frequency domain chaotic cognitive radioRuolin Zhou, Xue Li, Jian Zhang, Zhiqiang Wu 0001. 259-264 [doi]
• Configurable baseband designs and implementations of WiMAX/LTE dual systems based on multi-core DSPJen-Yuan Hsu, Chien-Yu Kao, Ping-Heng Kuo, Pangan Ting. 265-271 [doi]
• Tutorial: "Manufacturing test of systems-on-a-chip (SoCs)"Jacob A. Abraham. 272 [doi]
• Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenonHsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, An-Yeu Wu. 273-277 [doi]
• Fair rate packet arbitration in Network-on-ChipFalko Guderian, Erik Fischer, Markus Winter 0002, Gerhard Fettweis. 278-283 [doi]
• Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systemsChih-Hao Chao, Tsu-Chu Yin, Shu-Yen Lin, An-Yeu Wu. 284-289 [doi]
• TSV-based 3D-IC placement for timing optimizationYi-Rong Chen, Hung-Ming Chen, Shih-Ying Liu. 290-295 [doi]
• Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuitsYi-Xue Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li. 296-301 [doi]
• Exploring Virtual-Channel architecture in FPGA based Networks-on-ChipYe Lu, John V. McCanny, Sakir Sezer. 302-307 [doi]
• A novel methodology for Multi-Project System-on-a-ChipChih-Chyau Yang, Nien-Hsiang Chang, Shih-Lun Chen, Wei-De Chien, Chi-Shi Chen, Chien-Ming Wu, Chun-Ming Huang. 308-311 [doi]
• VFSMC - a core for cycle accurate multithreaded processing in hard real-time Systems-on-ChipSiegfried Brandstätter, Mario Huemer. 312-317 [doi]
• An analog gamma correction method for high dynamic range applicationsYuan Cao, Amine Bermak. 318-322 [doi]
• Low power tri-state register files design for modern out-of-order processorsNa Gong, Geng Tang, Jinhui Wang, Ramalingam Sridhar. 323-328 [doi]
• Instruction set customization for area-constrained FPGA designsAlok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan. 329-334 [doi]
• HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architectureAlexander Thomas, Michael Rückauer, Jürgen Becker. 335-340 [doi]
• Compiler-assisted technique for rapid performance estimation of FPGA-based processorsYan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan. 341-346 [doi]
• High performance multi-engine regular expression processingThianantha Arumugam, Sakir Sezer, Dwayne Burns, Vishalini Vasu. 347-352 [doi]
• Tutorial: "Design of high-speed wireline transceivers"Jri Lee. 353 [doi]
• A single-phase energy metering SoC with IAS-DSP and ultra low power metering modeYan Zhao, Nianxiong Tan, Kun Yang, Shupeng Zhong, Changyou Men. 354-358 [doi]
• PVT variations aware optimal sleep vector determination of dual VT domino OR circuitsNa Gong, Jinhui Wang, Ramalingam Sridhar. 359-364 [doi]
• Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuitsHailong Jiao, Volkan Kursun. 365-370 [doi]
• An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applicationsTzu-Chun Shih, Tsan-Wen Chen, Wei-Hao Sung, Ping-Yuan Tsai, Chen-Yi Lee. 371-375 [doi]
• Design of a neural recording amplifier with tunable pseudo resistorsKai-Wen Yao, Cihun-Siyong Alex Gong, Shan-Ci Yang, Muh-Tian Shiue. 376-379 [doi]
• Efficient design and synthesis of decimation filters for wideband delta-sigma ADCsRajaram Mohan Roy Koppula, Sakkarapani Balagopal, Vishal Saxena. 380-385 [doi]
• Technology trends and implications on SoC designJeffrey L. Burns. 386 [doi]
• The pending arrival of Phase Change Memory: The implications on the memory-storage hierarchy and on future systems developmentStefanie Chiras. 387 [doi]
• Floorplanning challenges in early chip planningJeonghee Shin, John A. Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy. 388-393 [doi]