Abstract is missing.
- Computer architecture for die stackingGabriel H. Loh. 1-2 [doi]
- A slew rate self-adjusting 2×VDD output buffer With PVT compensationChih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang. 1-4 [doi]
- Emerging touch techniques in smart handheld deviceLin Lin, Weber Chien. 1-2 [doi]
- Peak wake-up current estimation at gate-level with standard library informationMu-Shun Matt Lee, Yi-Chu Liu, Wan-Rong Wu, Chien-Nan Jimmy Liu. 1-4 [doi]
- A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOSTakumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto. 1-4 [doi]
- The best SoC solution with AndesCore and Andes's platformSimon Jiang, Frankwell lin. 1-4 [doi]
- Design validation on multiple-core CPU supported low power states using platform based infrared emission microscopy (PIREM) techniqueYuan-Chuan Steven Chen, Dave Budka, Auston Gibertini, Dan Bockelman, Yutien Lin. 1-4 [doi]
- Review of 3D high density storage class memory (SCM) architectureBrian Lee. 1 [doi]
- Statistical SDFC: A metric for evaluating test quality of small delay faultsXuefeng Zhu, Huawei Li, Xiaowei Li 0001. 1-4 [doi]
- On investigation into A CMOS-process-based high-voltage driver applied to implantable microsystemCihun-Siyong Alex Gong, Kai-Wen Yao, Jyun-Yue Hong, Muh-Tian Shiue. 1-4 [doi]
- Transforming memory systems: Optimizing for client value on emerging workloadsKevin J. Nowka. 1-2 [doi]
- Test for more than pass/fail using on-chip temperature sensorChih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu. 1-4 [doi]
- An efficient memory controller for 3D heterogeneous integration platformYi-Jun Liu, Chih-Chyau Yang, Shih-Lun Chen, Chun-Chieh Chiu, Chun-Chieh Chu, Chien-Ming Wu, Chun-Ming Huang. 1-4 [doi]
- 3D-IC BISR for stacked memories using cross-die sparesChun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin. 1-4 [doi]
- Universal architecture prototype for patient-centric medical environmentYun-Yen ChenWu, Hsi-Pin Ma, Chaitali Biswas, Dejan Markovic. 1-4 [doi]
- ForewordAn-Yeu Wu, Li-C. Wang. 1-2 [doi]
- Hardware-efficient true motion estimator based on Markov Random Field motion vector correctionFu-Chen Chen, Yung-Lin Huang, Shao-Yi Chien. 1-4 [doi]
- Silicon Carbide devices open a new era of power electronicsHidemi Takasu. 1-2 [doi]
- A fault-tolerant PE array based matrix multiplier designB.-Y. Jan, J.-L. Huang. 1-4 [doi]
- Data mining based prediction paradigm and its applications in design automationMagdy S. Abadir, Nik Sumikawa, Wen Chen, Li-C. Wang. 1 [doi]
- A master-slave SoC structure for HMM based speech recognitionHui Geng, Yiyu Shi, Ming Dong, Runsheng Liu. 1-4 [doi]
- A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swingTao Jiang, Kangmin Hu, Patrick Yin Chiang. 1-4 [doi]
- A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip linesChun-Lin Ko, Chieh-Pin Chang, Chien-Nan Kuo, Da-Chiang Chang, Ying-Zong Juang. 1-4 [doi]
- A highly parallel design of image surface layout recovering on GPGPUGuan-Ru Li, Bo-Cheng Charles Lai. 1-4 [doi]
- New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS processChih-Ting Yeh, Ming-Dou Ker. 1-4 [doi]
- Emerging memory technology perspectiveRoberto Bez, Paolo Cappelletti. 1-2 [doi]
- Gaining 10x in energy efficiency in the next decade in consumer productsPhilippe Magarshack, Andreia Cathelin. 1-2 [doi]
- Challenges and solutions in modern analog placementTung-Chieh Chen, Ta-Yu Kuan, Chung-Che Hsieh, Chi-Chen Peng. 1-4 [doi]
- An OCP-AHB bus wrapper with built-in ICE support for SOC integrationCheng-Ta Wu, Feng-Xiang Huang, Kuan-Fu Kuo, Ing-Jer Huang. 1-4 [doi]
- An energy-saving spectrum sensing processor based on partial discrete wavelet packet transformChih-Kai Yang, Chi-Hsuan Hsieh, Yuan-Hao Huang. 1-4 [doi]
- A fully-parallel step-by-step BCH decoder over composite field for NOR flash memoriesYi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang. 1-4 [doi]
- A highly integrated class-D amplifier using driver delay hysteresis controlJia-Nan Tai, Hsin-Shu Chen, Hang-Quei Chiu. 1-4 [doi]
- Ambient electronics and ultra-low power LSI designTakayasu Sakurai. 1-31 [doi]
- A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanismChing-Hwa Cheng, Jiun-In Guo. 1-4 [doi]
- An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM arrayYi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih. 1-4 [doi]
- VLSI CAD for emerging nanolithographyDavid Z. Pan, Jhih-Rong Gao, Bei Yu. 1-4 [doi]
- 3D IC test scheduling using simulated annealingChih-Yao Hsu, Chun-Yi Kuo, James Chien-Mo Li, Krishnendu Chakrabarty. 1-4 [doi]
- The 2012 ARM powered compute subsystem - delivering the smart handheld platformTim Whitfield. 1 [doi]
- High speed DDR2/3 PHY and dual CPU core design for 28nm SoCKevin Ho, Tsung-Yi Chou, Po-Kai Chen, David J. Liou. 1-5 [doi]
- Technology and design challenges for smartphone SOCsK. Lawrence Loh. 1 [doi]
- Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithmNasirul Chowdhury, Jeff Wight, Christopher Mozak, Nasser A. Kurd. 1-4 [doi]
- A range extending delay-recycled clock skew-compensation and/or duty-cycle-correction circuitShih-Nung Wei, Yi-Ming Wang, Jyun-Hua Peng, Yuandi Surya. 1-4 [doi]
- Powerful smartphone solutions unleashing new technology innovationsGary Huang. 1 [doi]
- Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aidsChing-Hao Lin, Kuo-Chiang Chang, Ming-Hsun Chuang, Chih-Wei Liu. 1-4 [doi]
- Wireless power link design using silicon-embedded inductors for brain-machine interfaceRongxiang Wu, Salahuddin Raju, Mansun Chan, Johnny K. O. Sin, C. Patrick Yue. 1-4 [doi]
- A power management technology for mobile embedded systemShui-An Wen, Chun-Chin Chen, Shing-Wu Tung. 1-4 [doi]
- Design of a pipelined clos network with late release schemeWeiXiang Tang, Yursun Hsu. 1-4 [doi]
- A 10-bit 200-MS/s reconfigurable pipelined A/D converterChia-Chi Ho, Tai-Cheng Lee. 1-4 [doi]
- Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM arrayMing-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang. 1-4 [doi]
- Routing-efficient implementation of an internal-response-based BIST architectureWei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee. 1-4 [doi]
- A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technologyChing-Che Chung, Duo Sheng, Wei-Da Ho. 1-4 [doi]
- ASIC synthesis using Architecture Description LanguageZheng Wang, Xiao Wang, Anupam Chattopadhyay, Zoltan Endre Rakosi. 1-4 [doi]
- Efficient architecture for Reed-Solomon decoderYung-Kuei Lu, Ming-Der Shieh. 1-4 [doi]
- An energy-efficient ultra-wideband transmitter with an FIR pulse-shaping filterWei-Ning Liu, Tsung-Hsien Lin. 1-4 [doi]
- Spatial-correlation-aware soft error rate analysis using quasi-importance samplingXin-Tian Wu, Kai-Hua Hsu, Lynn C.-L. Chang, Charles H.-P. Wen. 1-4 [doi]
- The evolution of fabless IC industry in China: Past, present, and futurePing K. Ko, C. Patrick Yue. 1 [doi]
- Google's C/C++ toolchain for smart handheld devicesDoug Kwan, Jing Yu, Bhaskar Janakiraman. 1-4 [doi]
- A 1-V, 44.6 ppm/°C bandgap reference with CDS techniquePeng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Chin Fu Lin. 1-4 [doi]
- A fast-locking phase-locked loop using CP control and gated VCOI-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu. 1-4 [doi]
- A monolithic 1.85GHz 2-stage sige power amplifier with envelope tracking for improved linear power and efficiencyRuili Wu, Yan Li 0008, Jerry Lopez, Donald Y. C. Lie. 1-4 [doi]
- 3-D centric technology and realization with TSVChang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou. 1-4 [doi]
- A novel design methodology for hybrid process 3D-ICChien-Lin Huang, Nian-Shyang Chang, Chi-Shi Chen, Chun-Pin Lin, Chien-Ming Wu, Chun-Ming Huang. 1-4 [doi]
- Power semiconductor-driving technology for high power green electronic systemsLeo Lorenz. 1-2 [doi]
- Low bandwidth HD1080@60FPS JPEG-XR transform designSheng-Wei Fan, Jia-Wai Chen, Jiun-In Guo. 1-4 [doi]
- Advances in computingYa-Qin Zhang. 1 [doi]
- Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier designKuei-Cheng Lin, Hwann-Kaeo Chiou, Po-Chang Wu, Chu-Jung Sha, Chun-Lin Ko, Da-Chiang Chang, Ying-Zong Juang. 1-4 [doi]
- Design and implementation of an optical OFDM baseband receiver in FPGAYin-Tsung Hwang, Sung-Jun Tsai, Yi-Yo Chen. 1-4 [doi]
- A nonlinear optimization methodology for resistor matching in analog integrated circuitsSheng-Jhih Jiang, Chan-Liang Wu, Tsung-Yi Ho. 1-4 [doi]
- Performance validation of dynamic-remapping-based task scheduling on 3D multi-core processorsChien-Hui Liao, Hung-Pin Wen. 1-4 [doi]
- An area-efficient CMOS switching converter with on-chip LC filter using feedforward ripple cancellation techniquePo-Hsiang Lan, Yao-Jun Kuo, Po-Chiun Huang. 1-4 [doi]
- DVB-T2 LDPC decoder with perfect conflict resolutionXiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto. 1-4 [doi]
- IMITATOR: A deterministic multicore replay system with refining techniquesShing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone, Tien-Fu Chen. 1-4 [doi]
- Design of a real-time software-based GPS baseband receiver using GPU accelerationJyun-Cheng Wu, Lei Chen, Tzi-Dar Chiueh. 1-4 [doi]
- Large set construction of user uplink ranging codes for M2M applicationsXi-Rui Wang, Hsi-Pin Ma, Jen-Yuan Hsu, Pangan Ting. 1-4 [doi]
- Port assignment for interconnect reduction in high-level synthesisCong Hao, Song Chen, Takeshi Yoshimura. 1-4 [doi]
- Post-bond test techniques for TSVs with crosstalk faults in 3D ICsYu-Jen Huang, Jin-Fu Li, Che-Wei Chou. 1-4 [doi]
- Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic propertyRuo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan Chien Fang, Chia-Chien Weng. 1-4 [doi]
- A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANsWei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang. 1-4 [doi]
- Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensorKuo-Wei Cheng, Chin Yin, Chih-Cheng Hsieh, Wen-Hsu Chang, Hann-Huei Tsai, Chin-Fong Chiu. 1-4 [doi]
- Disruptive technologies for the future generation smart systemsPeter Lemmens. 1 [doi]
- A hardware in the loop design methodology for FPGA system and its application to complex functionsGuixuan Liang, Danping He, Jorge Portilla, Teresa Riesgo. 1-4 [doi]
- Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systemsKun-Chih Chen, Chih-Hao Chao, Shu-Yen Lin, Hui-Shun Hung, An-Yeu Wu. 1-4 [doi]
- Area and reliability efficient ECC scheme for 3D RAMsLi-Jung Chang, Yu-Jen Huang, Jin-Fu Li. 1-4 [doi]
- A low cost DPA-resistant 8-bit AES core based on ring oscillatorsHsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee. 1-4 [doi]
- A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascodeTzon-Tzer Lu, Hua-Chin Lee, Chao-Shiun Wang, Chorng-Kuang Wang. 1-4 [doi]
- A 363-µW/fps power-aware green multimedia processor for mobile applicationsChi-Cheng Ju, Yung-Chang Chang, Chih-Ming Wang, Chun-Chia Chen, Hue-Min Lin, Chia-Yun Cheng, Fred Chiu, Sheng-Jen Wang, Tsu-Ming Liu, Chung-Hung Tsai. 1-4 [doi]
- Welcome from the general chairsMichel Brillouët, Shyh-Jye Jou, C. Patrick Yue. 1 [doi]
- 40MHz Gm-C filter with high linearity OTA for wireless applicationsShin-Jye Hsu, Che-Yu Lu, Chung-Chih Hung. 1-4 [doi]
- A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC arrayXiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda. 1-4 [doi]
- A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniquesJen-Huan Tsai, Yen-Ju Chen, Yan-Fong Lai, Meng-Hung Shen, Po-Chiun Huang. 1-4 [doi]
- A lossless embedded compression codec engine for HD video decodingLiang-Chi Chiu, Tian-Sheuan Chang. 1-4 [doi]