Shing-Wu Tung - researchr alias

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Viewing Publication 1 - 17 from 17

2013

A case study: 3-D stacked memory system architecture exploration by ESL virtual platformHsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai. vlsi-dat 2013: 1-4 [doi]

A 42.5µW/MHz ultra-low power 32-bit microcontroller - SPARKWei-Xiang Tang, Shui-An Wen, Shing-Wu Tung, Keng-Yu Lin, Chun-Chih Chen, Ching-Lung Su. IEEEicics 2013: 1-4 [doi]

2012

Low power and high performance 3-D multimedia platformPo-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung. hotchips 2012: 1-3 [doi]

A power management technology for mobile embedded systemShui-An Wen, Chun-Chin Chen, Shing-Wu Tung. vlsi-dat 2012: 1-4 [doi]

2011

Low power design and dynamic power management system for VLIW DSP subsystemHsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung. ispacs 2011: 1-5 [doi]

Heterogeneous Multi-core SoC Implementation with System-Level Design MethodologyJen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng. hpcc 2011: 851-856 [doi]

2003

SoC design integration by using automatic interconnection rectificationChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. iscas 2003: 744-747 [doi]

An automatic interconnection rectification technique for SoC design integrationChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. aspdac 2003: 108-111 [doi]

Automatic interconnection rectification for SoC design verification based on the port order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. tcad, 22(1):104-114, 2003. [doi]

2002

On automatic-verification pattern generation for SoC withport-order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. tcad, 21(4):466-479, 2002. [doi]

An automorphic approach to verification pattern generation for SoC design verification using port-order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. tcad, 21(10):1225-1232, 2002. [doi]

2001

1998

Verification Pattern Generation for Core-Based Design Using Port Order Fault ModelShing-Wu Tung, Jing-Yang Jou. ats 1998: 402-407 [doi]

A Logical Fault Model for Library Coherence CheckingShing-Wu Tung, Jing-Yang Jou. jise, 14(3):567-586, 1998. [doi]

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