Table of Contents

• System-on-Chip: Embedded Test StrategiesYervant Zorian. 7 [doi]
• Design and Test of Low Voltage CMOS CircuitsKaushik Roy, Ali Keshavarzi. 7 [doi]
• Redundancy Requirements for Embedded MemoriesMo Tamjidi, Bejoy G. Oomman. 8 [doi]
• Design Metrics to Achieve Design QualityAndrew B. Kahng, Ronald Collett, Ton. H. van de Kraats. 9 [doi]
• Fundamental Methods to Enable SoC Design and ReusePhil Dworsky, Warren Savage. 9 [doi]
• Issues in Deep Submicron State-of-the-Art ESD DesignCharvaka Duvvury. 10 [doi]
• Application of Formal Verification to Design Creation and ImplementationNoel R. Strader, Gérard Memmi, Carl Pixley. 11 [doi]
• Verification and Validation of Complex Digital Systems: An Industrial PerspectiveMagdy S. Abadir, Li-C. Wang. 11-12 [doi]
• Interconnect Modeling for Timing, Signal Integrity and ReliabilityNarain Arora, N. S. Nagaraj. 13 [doi]
• Re-Connecting MOS Modeling and Circuit Design: New Methods for Design QualityDaniel Foty, David Binkley. 13 [doi]
• On-Chip Inductance Extraction and ModelinDavid Blaauw, Rajendran Panda. 14 [doi]
• The 50-Million Transistor Chip: The Quality Challenge for 2001Rick Merritt, Richard Goering. 15 [doi]
• Monterey DesignTak Young. 19-20 [doi]
• Future Platform for Mobile CommunicationHajimi Sasaki. 21-22 [doi]
• Delivering Quality Delivers ProfitsJoe Costello. 23-24 [doi]
• The Expanding Use of Formal Techniques in Electronic DesignRaul Camposano. 25-26 [doi]
• IC Design Methodology in the Foundry Era: Introducing , Heads-Up(tm) DesignEdward C. Ross. 27 [doi]
• Stopping Criteria Comparison: Towards High Quality Behavioral VerificationAmjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman. 31-37 [doi]
• Concrete Impact of Formal Verification on Quality in IP Design and ImplementationUmberto Rossi, Andrea Fedeli, Marco Boschini, Franco Toto. 38-43 [doi]
• Simulation Using Code-Perturbation: Black- and White-Box ApproachZan Yang, Byeong Min, Gwan Choi. 44-49 [doi]
• A Design for Verification MethodologyF. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi. 50-55 [doi]
• A Hardware and Software Monitor for High-Level System-on-Chip VerificationMohammed El Shobaki, Lennart Lindh. 56 [doi]
• Techniques that Improved the Timing Convergence of the Gekko PowerPC MicroprocessorPaul Kartschoke, Shervin Hojat. 65-70 [doi]
• I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/OsGulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous. 71-75 [doi]
• Applying Moore s Technology Adoption Life Cycle Model to Quality of EDA SoftwareGiora Ben-Yaacov, Edward P. Stone, Richard Goldman. 76-80 [doi]
• A System for Automatic Recording and Prediction of Design Quality MetricsAndrew B. Kahng, Stefanus Mantik. 81-86 [doi]
• Scripting for EDA Tools: A Case StudyPinhong Chen, Kurt Keutzer, Desmond Kirkpatrick. 87 [doi]
• High Quality Analog CMOS and Mixed Signal LSI DesignAkira Matsuzawa. 97-104 [doi]
• CAD Issues for CMOS VLSI Design in SOIKenneth L. Shepard. 105-110 [doi]
• Foundry s Perspective of System Integration: Quality Design and Time-to-VolumeSheldon Wu, Fred Wang, Lie-Szu Juang. 111-116 [doi]
• Analysis and Design of ESD Protection Circuits for High-Frequency/RF ApplicationsChoshu Ito, Kaustav Banerjee, Robert W. Dutton. 117-122 [doi]
• Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability EffortsJ. W. McPherson. 123 [doi]
• A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit ModelNinglong Lu, Ibrahim N. Hajj. 133-138 [doi]
• A Model for Crosstalk Noise Evaluation in Deep Submicron ProcessesPirouz Bazargan-Sabet, Fabrice Ilponse. 139-144 [doi]
• Noise Model for Multiple Segmented Coupled RC InterconnectsAndrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani. 145-150 [doi]
• New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC TreesQingjian Yu, Ernest S. Kuh. 151-157 [doi]
• A Global Driver Sizing Tool for Functional Crosstalk Noise AvoidanceMurat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj. 158 [doi]
• Models For Interconnect Capacitance ExtractionAsim Husain. 167-172 [doi]
• Impact of On-Chip Inductance When Transitioning from Al to Cu Based TechnologyTom Chen. 173-178 [doi]
• Computational Cost Reduction in Extracting InductanceYusuke Nakashima, Makoto Ikeda, Kunihiro Asada. 179-184 [doi]
• Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater InsertionYu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie. 185-190 [doi]
• Signal Attenuation in Transmission LinesMehdi M. Mechaik. 191 [doi]
• Memory Bus Encoding for Low Power: A TutorialWei-Chung Cheng, Massoud Pedram. 199-204 [doi]
• RC Power Bus Maximum Voltage Drop in Digital VLSI CircuitsGeng Bai, Sudhakar Bobba, Ibrahim N. Hajj. 205-210 [doi]
• Instruction Prediction for Step Power ReductionZhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa. 211-216 [doi]
• Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology GenerationsRongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes. 217-222 [doi]
• A Compact Layout Technique for Reducing Switching Current Effects in High Speed CircuitsJuan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez. 223 [doi]
• 0.13 micron: Will the Speed Bumps Slow the Race to Market?Bill Alexander, Jacques Benkoski. 229 [doi]
• Quality of Design from an IC Manufacturing PerspectiveWojciech Maly. 235-236 [doi]
• Embedded Test Leads to Embedded QualityVinod Agrawal. 237-238 [doi]
• Quality on TimeAki Fujimura. 239-240 [doi]
• Quality of SoC Designs through Quality of the Design Flow: Status and NeedsPhilippe Magarshack. 241 [doi]
• Soft Core Based Model of a Microcomputer FamilyNguyen Quang Trung, Krystyna Siekierska. 245-246 [doi]
• Design on ESD Protection Circuit with Very Low and Constant Input CapacitanceTung-Yang Chen, Ming-Dou Ker. 247-248 [doi]
• Diversity Techniques for Concurrent Error DetectionSubhasish Mitra, Edward J. McCluskey. 249-250 [doi]
• Refinements of Rent s Rule Allowing Accurate Interconnect Complexity ModelingPeter Verplaetse. 251-252 [doi]
• Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer LevelVlado Vorisek. 253-254 [doi]
• Design, Integration and Validation of Heterogeneous SystemsS. Klupsch. 255-256 [doi]
• RC Power Bus Maximum Voltage Drop in Digital VLSI CircuitsGeng Bai, Sudhakar Bobba, Ibrahim N. Hajj. 257 [doi]
• Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS ProcessMing-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S. S. Chen, M.-C. Wang. 267-272 [doi]
• One Approach to Analog System Design Problem FormulationAlexander Zemliak. 273-278 [doi]
• VSIA Quality Metrics for IP and SoCMark Birnbaum, Charlene C. Johnson. 279-283 [doi]
• Hot-carrier-Induced Circuit Degradation for 0.18 ?m CMOS TechnologyWei Li, Qiang Li, J. S. Yuan, Joshua McConkey, Yuan Chen, Sundar Chetlur, Jonathan Zhou, A. S. Oates. 284-289 [doi]
• Verification of Embedded Phase-Locked LoopsTom Egan, Samiha Mourad. 290-295 [doi]
• An Effective Current Source Cell Model for VDSM Delay CalculationAlexander Korshak, Jyh-Chwen Lee. 296-300 [doi]
• An Evaluation of Single-Ended and Differential Impedance in PCBsMehdi M. Mechaik. 301-306 [doi]
• HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability AnalysisYi-Min Jiang, Han Young Koh, Kwang-Ting Cheng. 307-312 [doi]
• Power Grid Modeling Technique for Hierarchical Power Network AnalysisNing Zhu, Han Young Koh. 313-318 [doi]
• Energy Efficient Signaling in Deep Submicron CMOS TechnologyImed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi. 319-324 [doi]
• Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor DesignRong Lin. 325-330 [doi]
• Complex Reliability Evaluation of Voters for Fault Tolerant DesignsMihaela Radu, Dan Pitica, Radu Munteanu, Cristian Posteuca. 331-336 [doi]
• Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling FlowJosef Schmid, Timo Schüring, Christoph Smalla. 337-342 [doi]
• An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in DatapathsNektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. 343-349 [doi]
• On Accumulator-Based Bit-Serial Test Response Compaction SchemesDimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos. 350 [doi]
• Revisiting the Classical Fault Models through a Detailed Analysis of Realistic DefectsMichel Renovell. 359-364 [doi]
• Defect-Oriented Fault Simulation and Test Generation in Digital CircuitsWieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar. 365-371 [doi]
• Automatic Functional Vector Generation Using the Interacting FSM ModelChien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou. 372-377 [doi]
• Color Counting and its Application to Path Delay Fault CoverageJayant Deodhar, Spyros Tragoudas. 378-383 [doi]
• ATPG for Path Delay Faults without Path EnumerationMaria K. Michael, Spyros Tragoudas. 384 [doi]
• HW-SW Co-Design and Verification of a Multi-Standard Video and Image CodecRafael Peset Llopis, Marcel Oosterhuis, Ramanathan Sethuraman, Paul E. R. Lippens, Albert van der Werf, Steffen Maul, Jim Lin. 393-398 [doi]
• Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral SynthesisMartin Speitel, Michael Schlicht, Martin Leyh. 399-404 [doi]
• ELITE Design Methodology of Foundation IP for Improving Synthesis QualityChih-Yuan Chen, Shing-Wu Tung. 405-408 [doi]
• High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship MeasuresArtur Chojnacki, Lech Józwiak. 409-414 [doi]
• Implementation of Multipliers in FPGA StructuresKazimierz Wiatr, Ernest Jamro. 415 [doi]
• Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life?Nader Vasseghi, Steve Ohr. 421 [doi]
• Early Detection of Design Sensitivities that Cause Yield Loss for New ProductsRon Ross, Keith McCasland. 427-430 [doi]
• Assessment of True Worst Case Circuit Performance Under Interconnect Parameter VariationsEmrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu. 431-436 [doi]
• Timing Yield Estimation from Static Timing AnalysisAnne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long. 437-442 [doi]
• Performance Improvement for High Speed Devices Using E-tests and the SPICE ModelTae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, Jeong-Taek Kong. 443 [doi]
• A Fully Qualified Analog Design Flow for Non Volatile Memories TechnologiesPierluigi Daglio, M. Araldi, M. Morbarigazzi, Carlo Roma. 451-455 [doi]
• Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas. 456-461 [doi]
• A Method of Embedded Memory Access Time MeasurementNai-Yin Sung, Tsung-Yi Wu. 462 [doi]
• Noise in Radio Frequency Circuits: Analysis and Design ImplicationsAmit Mehrotra. 469-476 [doi]
• Spice Model Quality: Process Development ViewpointPeter Bendix. 477-481 [doi]
• Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix ComputationYoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata. 482-487 [doi]
• Modeling of Substrate Noise Injected by Digital LibrariesStefano Zanella, Andrea Neviani, Enrico Zanoni, Paolo Miliozzi, Edoardo Charbon, Carlo Guardiani, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 488 [doi]