Jacques Benkoski - researchr alias

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Viewing Publication 1 - 15 from 15

2007

Do Digital Design and Variability Mix like Oil and Water?Jacques Benkoski, Michelle Clancy, Shankar Krishnamoorthy, David Holt, Ravi Subramanian, Clive Bittlestone, Tsuyoshi Yamamoto, Andrew Kanhg. isqed 2007: 672-676 [doi]

2002

Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC DesignsK. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment. date 2002: 538-539 [doi]

2001

0.13 micron: Will the Speed Bumps Slow the Race to Market?Bill Alexander, Jacques Benkoski. isqed 2001: 229 [doi]

2000

How Do You Select A High Quality EDA Tool Flow?Robert N. Blair, Jacques Benkoski. isqed 2000: 17 [doi]

1993

Demosthenes-A technology-independent power DMOS layout generatorG. Fourneris, N. Bekkara, Jacques Benkoski, L. Zullino, D. Spatafora, G. Martino. eurodac 1993: 178-183 [doi]

Yield optimization of analog ICs using two-step analytic modeling methodsCarlo Guardiani, Primo Scandolara, Jacques Benkoski, Germano Nicollini. jssc, 28(7):778-783, July 1993. [doi]

1992

Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulationRonald B. Stewart, Véronique Anjubault, Philippe Garcin, Jacques Benkoski. eurodac 1992: 28-31 [doi]

1991

1990

Timing verification using statically sensitizable pathsJacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man. tcad, 9(10):10723-10784, 1990. [doi]

1989

Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing SimulatorJacques Benkoski, Andrzej J. Strojwas. dac 1989: 668-673 [doi]

Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing SimulatorJacques Benkoski, Andrzej J. Strojwas. itc 1989: 153-160

1987

A New Approach to Hierarchical and Statistical Timing SimulationsJacques Benkoski, Andrzej J. Strojwas. tcad, 6(6):1039-1052, 1987. [doi]

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