Table of Contents

• Fast functional evaluation of candidate OBDD variable orderingsDon E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer. 4-10 [doi]
• Resolution-based correctness proofs of synchronous circuitsPaolo Camurati, Tiziana Margaria, Paolo Prinetto. 11-15 [doi]
• Correct interactive transformational synthesis of DSP hardwareFrank P. Burns, D. J. Kinniment, Albert Koelmans. 16-21 [doi]
• Verification of synthesized circuits at register transfer level with flow graphsFridtjof Feldbusch, Ramayya Kumar. 22-26 [doi]
• Tool communication in an integrated synthesis environmentBernd Kleinjohann, Elisabeth Kupitz. 28-32 [doi]
• A distributed engineering database management system for IC designWanlin Cao, Y. Edmund Lien, Yuane Qiu, Li Shao. 33-37 [doi]
• An approach to design flow management in CAD frameworksMahesh Mehendale. 38-42 [doi]
• Why to incorporate a data definition language into a CAD frameworks extension languageKlaus Gröning, Walter Heijenga. 43-47 [doi]
• On variable ordering of binary decision diagrams for the application of multi-level logic synthesisMasahiro Fujita, Yusuke Matsunaga, Taeko Kakuda. 50-54 [doi]
• PHIFACT a design space exploration programF. Crowet, Marc Davio, C. Dierieck, J. Durieu, G. Louis, Chantal Ykman-Couvreur. 55-59 [doi]
• Synthesis of multi-level logic with one symbolic inputFrank Buijs, Thomas Lengauer. 60-64 [doi]
• PLATO: a CAD tool for logic synthesis based on decompositionTadeusz Luba, Jerzy Kalinowski, Krzysztof Jasinski. 65-69 [doi]
• An approach to the analysis and test of crosstalk faults in digital VLSI circuitsAntonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita. 72-79 [doi]
• Detection of PLA multiple crosspoint faultsM. Ambanelli, Michele Favalli, Piero Olivo, Bruno Riccò. 80-84 [doi]
• A probabilistic fault model for analog faultsMichele Favalli, Piero Olivo, Bruno Riccò. 85-88 [doi]
• The automatic diagnosis of faults in analogue and mixed-signal circuitsAlice McKeon, Antony Wakeling. 89-93 [doi]
• Formal sizing rules of CMOS circuitsDaniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert. 96-100 [doi]
• Delay estimation for CMOS functional cellsJan Madsen. 101-105 [doi]
• Electrical modelling of lossy on-chip multilevel interconnecting linesK. Z. Dimopoulos, John N. Avaritsiotis, S. J. White. 106-110 [doi]
• Restructuring VLSI layout representations for efficiencyRavi Nair, Vivek Chickermane, Ray Chamberlain. 111-116 [doi]
• Address Generation for array access based on modulus m countersDouglas M. Grant, Peter B. Denyer. 118-122 [doi]
• High level synthesis: a data path partitioning method dedicated to speed enhancementF. Monteiro, Bruno Rouzeyre, Georges Sagnes. 123-128 [doi]
• Datapath optimization using feedbackDavid W. Knapp. 129-134 [doi]
• Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulatorJoel Besnard, Jacques Benkoski, Bernard Hennion. 136-141 [doi]
• SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuitsShen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh. 142-148 [doi]
• Circuit partitioning for waveform relaxationWerner John, Werner Rissiek, Karl L. Paap. 149-153 [doi]
• Performance macromodelling and optimization of regular VLSI structuresP. Hallam, T. I. Pritchard, Gloria Childress Townsend. 154-159 [doi]
• Glue-logic partitioning for floorplans with a rectilinear datapathAllen C.-H. Wu, Daniel D. Gajski. 162-166 [doi]
• Towards optimizing global MinCut partitioningAchim G. Hoffmann. 167-171 [doi]
• SHARP-looking geometric partitioningS. Bapat, James P. Cohoon. 172-176 [doi]
• n pieces with a time-efficient net cost functionPaul Stravers. 177-182 [doi]
• Exact and heuristic algorithms for the minimization of incompletely specified state machinesGary D. Hachtel, June-Kyung Rho, Fabio Somenzi, Reily M. Jacoby. 184-191 [doi]
• Fast heuristic algorithms for finite state machine minimizationLalgudi N. Kannan, D. Sarma. 192-196 [doi]
• Formal method for self-timed designMichael Kishinevsky, Alex Kondratyev, Alexander Taubin. 197-201 [doi]
• Array folding using heuristics and simulated annealingLalgudi N. Kannan, D. Sarma. 202-205 [doi]
• Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environmentJos van Sas, Francky Catthoor, Peter Vandeput, Frank Rossaert, Hugo De Man. 208-213 [doi]
• HITEC: a test generation package for sequential circuitsThomas M. Niermann, Janak H. Patel. 214-218 [doi]
• On the selection of a partial scan path with respect to target faultsHarald Gundlach, Bernd K. Koch, Klaus-Dieter Müller-Glaser. 219-223 [doi]
• Model-based fault diagnosis of sequential circuits and its accelerationBenjamin Rogel-Favila, Antony Wakeling, Peter Y. K. Cheung. 224-229 [doi]
• An algorithm for improving optimal placement for river-routingSteven T. Healey. 232-236 [doi]
• An integrated layout system for sea-of-gates module generationP. Duchene, Michel J. Declercq, S. M. Kang. 237-241 [doi]
• A global router for sea-of-gates circuitsKai-Win Lee, Carl Sechen. 237-241 [doi]
• Mickey: a macro cell global routerDahe Chen, Carl Sechen. 248-252 [doi]
• TATOO: an industrial timing analyzer with false path elimination and test pattern generationJacques Benkoski, Ronald B. Stewart. 256-260 [doi]
• TAS: an accurate timing analyser for CMOS VLSIAmjad Hajjar, Alain Greiner, Roland Marbot, Payam Kiani. 261-265 [doi]
• A hierarchical approach to timing verification in CMOS VLSI designH. G. Yang, David M. Holburn. 266-270 [doi]
• Clock independent timing verification of level-sensitive latchesRobert Tjärnström. 271-275 [doi]
• Test scheduling and controller synthesis in the CADDY-systemMartin Rudolph, Michael Nether, Wolfgang Rosenstiel. 278-282 [doi]
• Synthesis of fully testable sequential machinesR. Thomas, S. Kundu. 283-288 [doi]
• MACHETE: synthesis of sequential machines for easy testabilityBapiraju Vinnakota, Niraj K. Jha. 289-293 [doi]
• Testability analysis of hierarchical finite state machinesFrançoise Martinolle, Jean Claude Geffroy, Bernard Soulas. 294-301 [doi]
• Area and performance optimizations in path-based schedulingReinaldo A. Bergamaschi, Raul Camposano, Michael Payer. 304-310 [doi]
• CASCH: a scheduling algorithm for "high level"-synthesisPeter Gutberlet, Heinrich Krämer, Wolfgang Rosenstiel. 311-315 [doi]
• Specification of timing constraints for controller synthesisRumi Zahir, Wolfgang Fichtner. 316-322 [doi]
• Parallel switch-level simulation for VLSIRobert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham. 324-328 [doi]
• Functional abstraction of logic gates for switch-level simulationDavid T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham. 329-333 [doi]
• Incremental switch-level simulation with zero/integer-delayLarry G. Jones. 334-338 [doi]
• On probabilistic switch-level simulation for asynchronous circuitsSuresh Rajgopal, Akhilesh Tyagi. 339-343 [doi]
• Floorplanning strategy for mixed analog-digital VLSI integrated circuitsLuis París, G. Berbel, T. Osés. 346-350 [doi]
• LAST: a Layout Area and Shape function esTimator for high level applicationsFadi J. Kurdahi, Champaka Ramachandran. 351-355 [doi]
• Efficient shape curve construction in floorplan designTing-Chi Wang, D. F. Wong. 356-360 [doi]
• Goal oriented slicing enumeration through shape function clippingGeorg Sigl, Ulf Schlichtmann. 361-365 [doi]
• Optimization of micro-controllers by partitioningG. Tarroux, Bruno Rouzeyre, Georges Sagnes. 368-373 [doi]
• A new decomposition method for multilevel circuit designD. Bochmann, F. Dresig, B. Steinbach. 374-377 [doi]
• Decomposing data machinesWayne Wolf. 378-382 [doi]
• The VLSI-programming language tangram and its translation into handshake circuitsKees van Berkel, Joep L. W. Kessels, Marly Roncken, Ronald Saeijs, Frits D. Schalij. 384-389 [doi]
• Translating system specifications to VHDLSanjiv Narayan, Frank Vahid, Daniel D. Gajski. 390-394 [doi]
• Formal methods for silicon compilationTon Kalker. 395-400 [doi]
• Data flow graphs: system specification with the most unrestricted semanticsGjalt G. de Jong. 401-405 [doi]
• GENVIEW: a portable source-level debugger for macrocell generatorsA. Compan, Alain Greiner, François Pêcheux, Frédéric Pétrot. 408-412 [doi]
• A framework for hierarchical performance analysisFarid Mheir-El-Saadi, Bozena Kaminska. 413-418 [doi]
• HERESY: a hybrid approach to automatic schematic generationTzi-cker Chiueh. 419-423 [doi]
• GRTL: a graphical platform for pipelined system designGlenn Jennings. 424-428 [doi]
• Improved force-directed schedulingWim F. J. Verhaegh, Emile H. L. Aarts, Jan H. M. Korst, Paul E. R. Lippens. 430-435 [doi]
• PHIDEO: a silicon compiler for high speed algorithmsPaul E. R. Lippens, Jef L. van Meerbergen, Albert van der Werf, Wim F. J. Verhaegh, B. T. McSweeney, Jos Huisken, O. McArdle. 436-441 [doi]
• Affine transformations for multi-dimensional signal processing on ASIC regular arraysJan Rosseel, Michaël F. X. B. van Swaaij, Francky Catthoor, Hugo De Man. 442-446 [doi]
• Switch and logic-level modeling in EDIF 200: limitations and proposed solutionsShankar R. Mukherjee, Maqsoodul Mannan. 448-452 [doi]
• Design of a persistent programming environment in an object oriented language using clustering and composite objectsMattie N. Sim, Patrick M. Dewilde. 453-458 [doi]
• A hardware design system based on object-oriented principlesA. J. van der Hoeven, Ed F. Deprettere, P. van Prooijen, Patrick M. Dewilde. 459-463 [doi]
• Design by similarity using transaction modeling and statistical techniquesAnas Kabbaj, Eduard Cerny, Michel Dagenais, François Bouthillier. 464-468 [doi]
• An automatic synthesizer for CMOS operational amplifiersChin-Yuan Kuo, Liang-Gee Chen, Tai-Ming Parng. 470-474 [doi]
• DONALD: a workbench for interactive design space exploration and sizing of analog circuitsKoen Swings, Willy Sansen. 475-479 [doi]
• A new approach to layout of custom analog cellsLouis-Oliver Donzelle, Pierre-François Dubois. 480-483 [doi]
• Interactive symbolic distortion analysis of analogue integrated circuitsPiet Wambacq, Georges G. E. Gielen, Willy Sansen. 484-488 [doi]
• Symbolic implication in test generationSandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar. 492-496 [doi]
• Structure based methods for parallel pattern fault simulation in combinational circuitsBernd Becker, Ralf Hahn, Rolf Krieger, Uwe Sparmann. 497-502 [doi]
• Experiments with autonomous test of PLAsEinar J. Aas, Gunnar Nystu. 503-509 [doi]
• A self-checking PLA automatic generator tool based on unordered codes encodingKholdoun Torki, Michael Nicolaidis, A. O. Fernandes. 510-515 [doi]
• Circuit partitioning into small sets: a tool to support testing with further applicationsSpyros Tragoudas, R. Farrell, Fillia Makedon. 518-522 [doi]
• Iterative compaction: an improved approach to graph and circuit bisectionJames Haralambides, Fillia Makedon. 523-527 [doi]
• k distinct row vectorsHongzhong Wu. 528-532 [doi]
• Technology mapping for a two-output RAM-based field programmable gate arrayDavid Filo, Jerry Chih-Yuan Yang, Frederic Mailhot, Giovanni De Micheli. 534-538 [doi]
• A fast and efficient algorithm for determining fanout trees in large networksShen Lin, Malgorzata Marek-Sadowska. 539-544 [doi]
• Optimization techniques for multiple output function synthesisGiacomo Buonanno, Donatella Sciuto, Renato Stefanelli. 545-551 [doi]
• Concurrent MIN-MAX simulationErnst G. Ulrich, Karen Panetta Lentz, Stephen R. Demba, Rahul Razdan. 554-557 [doi]
• Hybrid compiled/interpreted simulation of MOS circuitsLarry McMurchie, Craig Anderson, Gaetano Borriello. 558-564 [doi]
• Periodic signal suppression in a concurrent fault simulatorTara Weber, Fabio Somenzi. 565-569 [doi]
• A proposed hardware fault simulation engineDaniel Cock, Andy Carpenter. 570-574 [doi]
• A performance analysis tool for performance-driven micro-cell generationRafael Peset Llopis, R. J. H. Koopman, Hans G. Kerkhoff, J. A. Braat. 576-580 [doi]
• Module synthesis for finite state machinesA. Kuehlmann, Yiannos Manoli. 581-585 [doi]