Einar J. Aas - researchr alias

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Viewing Publication 1 - 34 from 34

2011

A programmable BIST with macro and micro codes for embedded SRAMsPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas, Mohammad Areef. ewdts 2011: 144-150 [doi]

Design of embedded TCAM based longest prefix match search enginePalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. mam, 35(8):659-667, 2011. [doi]

An Enhanced Path Delay Fault Simulator for Combinational CircuitsPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. dsd 2011: 375-381 [doi]

2010

Path-Delay Fault Testing in Embedded Content Addressable MemoriesPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. dsd 2010: 519-524 [doi]

Experiments with ABIST test methodology applied to path delay fault testingPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. ewdts 2010: 59-63 [doi]

2009

Design of novel CAM core cell structures for an efficient implementation of low power BCAM systemPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. glvlsi 2009: 57-62 [doi]

2008

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing ApplicationsPer Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas. vlsisp, 53(3):301-321, 2008. [doi]

Scan Test Response Compaction Combined with Diagnosis CapabilitiesSverre Wichlund, Frank Berntsen, Einar J. Aas. et, 24(1-3):235-246, 2008. [doi]

2007

Probabilistic gate-level power estimation using a novel waveform set methodSaeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas. glvlsi 2007: 37-42 [doi]

2006

Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactorSverre Wichlund, Frank Berntsen, Einar J. Aas. dft 2006: 119-127 [doi]

Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory CompactorSverre Wichlund, Einar J. Aas. ats 2006: 421-430 [doi]

2005

Remote Path Delay Fault SimulationOystein Gjermundnes, Einar J. Aas. dsdm 2005: 428-434 [doi]

2004

Storage requirement estimation for optimized design of data intensive applicationsPer Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas. todaes, 9(2):133-158, 2004. [doi]

2003

Data dependency size estimation for use in memory optimizationPer Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas. tcad, 22(7):908-921, 2003. [doi]

On the Utilization of Java Technology in Embedded SystemsØyvind Strøm, Kjetil Svarstad, Einar J. Aas. dafes, 8(1):87-106, 2003. [doi]

2001

Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive ApplicationsPer Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas. dac 2001: 365-370 [doi]

Formal verification of digital circuits by 3-valued simulationAyman M. Wahba, Einar J. Aas. icecsys 2001: 785-788 [doi]

An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java CodeØyvind Strøm, Einar J. Aas. dsdm 2001: 396-399 [doi]

2000

1999

Project based learning objectives and experiences in electronic education: a memory controller design experimentEinar J. Aas, Jukka Typpo. icecsys 1999: 1611-1614 [doi]

A Study of Dynamic Instruction Frequencies in Byte Compiled Java ProgramsØyvind Strøm, Audun Klauseie, Einar J. Aas. euromicro 1999: 1232-1235 [doi]

1996

4300 Megasamples/s Wave Digital Filter Implementation In Bit-parallel Tspc Circuit TechniqueJohnny Pihl, Einar J. Aas. isspa 1996: 668-671 [doi]

Comparison of two architectures for implementation of the discrete cosine transformIngil Sundsbo, G. Lokken Hansen, Einar J. Aas. icassp 1996: 3272-3275 [doi]

1994

Quantifying Design Quality Through Design ExperimentsEinar J. Aas, Tore Steen, Karl Klingsheim. dt, 11(1):27-38, 1994. [doi]

1993

Verification and Diagnosis of Digital Systems by Termary ReasoningAyman M. Wahba, Einar J. Aas. charme 1993: 55-67

1991

Experiments with autonomous test of PLAsEinar J. Aas, Gunnar Nystu. eurodac 1991: 503-509 [doi]

Combined probabilistic testability calculation and compact test generation for PLAsBjørg Reppen, Einar J. Aas. et, 2(3):215-227, 1991. [doi]

1990

State transition graph analysis as a key to BIST fault coverageOve Brynestad, Einar J. Aas, Anne E. Vallestad. itc 1990: 537-543 [doi]

1984

Test generation through logic programmingDag Svanæs, Einar J. Aas. integration, 2(1):49-67, 1984. [doi]

1978

An integrated system for interactive editing of schematics, logic simulation and PCB layout designHedayat Markus Bayegan, Einar J. Aas. dac 1978: 1-8 [doi]

1975

Design automation in norwayP. A. Arneberg, Einar J. Aas. dac 1975: 251-256 [doi]

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