Table of Contents

• An approach for PSL assertion coverage analysis with high-level decision diagramsMaksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova. 13-16 [doi]
• Secure communication protocol for wireless sensor networksDaniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra. 17-20 [doi]
• Hardware reduction for FSM - Based control units using PAL technologyAlexander Barkalov, Larysa Titarenko, Slawomir Chmielewski. 21-24 [doi]
• SAT-based group method for verification of logical descriptions with functional indeterminacyLiudmila D. Cheremisinova, Dmitry Ya. Novikov. 25-28 [doi]
• A process variation detection methodVazgen Melikyan, Davit Mirzoyan, Gor Petrosyan. 30-33 [doi]
• Architecture of queued-free crossbar for on-chip networksSargis Abovyan, Gor Petrosyan, Tigran Harutyunyan. 34-36 [doi]
• Modeling on-chip variations in digital circuits using statistical timing analysisGor Petrosyan, Sargis Abovyan, Tigran Harutyunyan. 37-39 [doi]
• Stable current and voltage generation under process variationV. Melikyan, S. Karapetyan, D. Mirzoyan, E. Babayan. 40-42 [doi]
• Self-testing of microcontrollers in the fieldJanusz Sosnowski. 43-46 [doi]
• Exploring modeling and testing of NAND flash memoriesStefano Di Carlo, Michele Fabiano, Roberto Piazza, Paolo Prinetto. 47-50 [doi]
• Coverage method for FPGA fault logic blocks by sparesVladimir Hahanov, Eugenia Litvinova, Wajeb Gharibi, Olesya Guz. 51-56 [doi]
• Experiments with ABIST test methodology applied to path delay fault testingPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. 59-63 [doi]
• Improving reliability for bit parallel finite field multipliers using Decimal HammingNikolaos Mavrogiannakis, Costas Argyrides, Dhiraj K. Pradhan. 69-72 [doi]
• Microprogram control unit with code sharing and extended microinstruction formatAlexander Barkalov, Larysa Titarenko, Jacek Bieganowski. 73-76 [doi]
• Testing and verification of HDL-models for SoC componentsVladimir Hahanov, Irina Hahanova, Ngene Christopher Umerah, Tiecoura Yves. 77-82 [doi]
• Metastability testing at FPGA circuit design using propagation time characterizationBranka Medved Rogina, Peter Skoda, Karolj Skala, Ivan Michieli, Maja Vlah, Sinisa Marijan. 80-85 [doi]
• Fault tolerance of decomposed PLAsOsnat Keren, Ilya Levin. 86-91 [doi]
• Verification of FPGA electronic designs for nuclear reactor trip systems: test- and invariant-based methodsA. Andrashov, Vyacheslav S. Kharchenko, Vladimir V. Sklyar, L. Reva, V. Dovgopolyi, V. Golovir. 92-97 [doi]
• Cyber space and brain-like computingVladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko. 98-109 [doi]
• Vector logic analysis of associative matricesVladimir Hahanov, Wajeb Gharibi, Svetlana Chumachenko, Eugenia Litvinova. 110-117 [doi]
• Table data structures for cyber spaceVladimir Hahanov, Eugenia Litvinova, Aleksey Priymak. 118-122 [doi]
• Process models for analyzing associative data structuresVladimir Hahanov, Olesya Guz, Ngene Christopher Umerah, Vitaliy Olchovoy. 123-127 [doi]
• A technique to accelerate the Vector Fitting algorithm for interconnect simulationMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov. 127-130 [doi]
• Frequency domain techniques for simulation of oscillatorsMark M. Gourary, Sergey G. Rusakov, Alexander L. Stempkovsky, Sergey L. Ulyanov, Michael M. Zharov. 131-134 [doi]
• Component-based safety-oriented on-line testing of digital systemsAlexander Drozd, Vyacheslav S. Kharchenko, Siora Alexandr, Vladimir V. Sklyar. 135-140 [doi]
• Generalized faulty block model for automatic test pattern generationF. Podyablonsky, N. Kascheev. 141-143 [doi]
• A technique of optimal built-in self-test circuitries generationNatalia V. Chebykina, Sergey G. Mosin. 145-148 [doi]
• Applied library of adaptive lattice filters for nonstationary signal processingVictor I. Djigan. 149-152 [doi]
• GA-based and design by contract approach to test generation for EFSMsAndrey Zakonov, Oleg Stepanov, Anatoly Shalyto. 152-155 [doi]
• Implementation of a new paradigm in design of IIR digital filtersVladislav A. Lesnikov, Tatiana V. Naumovich, Alexander V. Chastikov, Sergey V. Armishev. 156-159 [doi]
• PDFs testing of combinational circuits based on covering ROBDDsAnjela Matrosova, E. Nikolaeva. 160-163 [doi]
• Path delay faults and ENFAnjela Matrosova, V. Lipsky, Alexey Melnikov, Virendra Singh. 164-167 [doi]
• Test minimization technique for multiple stuck-at faults of combinational circuitValentina Andreeva. 168-170 [doi]
• Testable combinational circuit design based on ZDD-implementation of ISOP Boolean functionS. Ostanin, R. Muchamedov. 171-174 [doi]
• Level quantization effect on accuracy of fast Fourier transform algorithmG. S. Khanyan. 175-178 [doi]
• On-chip measurements of standard-cell propagation delayS. O. Churayev, B. T. Matkarimov, T. T. Paltashev. 179-181 [doi]
• FPGA FFT implementationS. O. Churayev, B. T. Matkarimov. 183-185 [doi]
• A method for automatic generation of an RTL-interface from a C++ descriptionVolodymyr Obrizan. 186-189 [doi]
• OFDM-based audio watermarking for electronic radiotelephone identificationAleksandr V. Shishkin. 190-194 [doi]
• Reconfiguration and hardware agents in testing and repair of distributed systemsGeorge Dan Mois, Iulia Stefan, Szilárd Enyedi, Liviu Miclea. 195-198 [doi]
• On selection of state variables for delay test of identical functional unitsAditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh. 200-203 [doi]
• Metrics of vector logic algebra for cyber spaceVladimir Hahanov, Alexander Mishchenko, Vitaliy Varetsa. 204-207 [doi]
• Cyber space evolutionVladimir Hahanov, Anna Hahanova, Vagan Zakaryan. 208-214 [doi]
• Logical method for detecting faults by fault detection tableVladimir Hahanov, Irina Pobizhenko, Tiecoura Yves. 215-217 [doi]
• EDACs and test integration strategies for NAND flash memoriesStefano Di Carlo, Michele Fabiano, Roberto Piazza, Paolo Prinetto. 218-221 [doi]
• Communication interface synthesis from TLM 2.0 to RTLNadereh Hatami, Marco Indaco, Paolo Prinetto, Gabriele Tiotto. 222-226 [doi]
• Sign Language synthesis using hand motion acquisitionNadereh Hatami, Paolo Prinetto, Gabriele Tiotto. 226-229 [doi]
• An algorithm of timing recovery for modem with M-ary alphabets APK-signalsVictor V. Panteleev. 230-235 [doi]
• Engineering-maintenance methods of the calculation xDSL-linesVictor V. Panteleev, Alexander I. Vakaruk. 236-241 [doi]
• Common-mode signal minimization in differential stageSergei G. Krutchinsky, Michael S. Tsibin, Alexey E. Titov. 242-245 [doi]
• Optimization of sensitivity dominating parameters OA in selective IP blocksSergei G. Krutchinsky. 246-249 [doi]
• Adaptive array based on "Multicore" DSP family and Linearly Constrained constant modulus IQRD RLS algorithmIrina D. Pletneva, Victor I. Djigan. 254-257 [doi]
• Performance investigation of antenna arrays by means of virtual instrumentsVictor I. Djigan. 258-261 [doi]
• Level quantization effects in digital signal processing by discrete Fourier transform methodG. S. Khanyan. 262-265 [doi]
• Internal structure of software application for controlling devices via JTAG 1149 interfaceIgor Ilyin, Rostislav Grushvitsky. 264-266 [doi]
• Straight edge extraction and localization on noisy imagesVladimir Volkov, Rudolf Germer, Alexandr Oneshko, Denis Oralov. 267-270 [doi]
• A digital implementation of multi-h CPM modemG. V. Kulikov, A. U. Unger, P. G. Suhanov. 271-273 [doi]
• Quantization step dispersion of direct transformation ADCStanislav S. Gritsutenko, Aleksey G. Panyukov. 274-277 [doi]
• th power of signal samplesAlexander B. Sergienko, Alexander V. Petrov. 278-281 [doi]
• A new paradigm in design of IIR digital filtersVladislav A. Lesnikov, Tatiana V. Naumovich, Alexander V. Chastikov, Sergey V. Armishev. 282-285 [doi]
• Evolutionary approach to test generation of sequential digital circuits with multiple observation time strategyY. A. Skobtsov, V. Y. Skobtsov. 286-291 [doi]
• Two-criterial DSSS synchronization method efficiency researchH. V. Kharchenko, I. O. Tkalich, Y. I. Vdovychenko. 289-299 [doi]
• An entropic approach to diagnostic information compressionDmitriy Speranskiy. 292-299 [doi]
• Dynamic characteristics of different system design strategiesAlexander Zemliak, M. Torres, F. Reyes, S. Vergara, T. M. Markina. 300-303 [doi]
• FPGA-based digital phase difference meterYegor I. Vdovychenko. 309 [doi]
• An efficient March test for detection of all two-operation dynamic faults from subclass SavH. Avetisyan, Gurgen Harutyunyan, Valery A. Vardanian, Yervant Zorian. 310-313 [doi]
• Component architecture with runtime type definitionE. M. Grinkrug, A. R. Shakurov. 315-318 [doi]
• New method of multi-level optimizationH. H. Asadov, Y. N. Aliyeva, L. A. Bayramova, K. Kh. Ismailov. 319-321 [doi]
• Utilization of variation optimization for location of emitter of random noise signalH. H. Asadov, N. A. Abdullayev, M. J. Kerimov, E. F. Dadashov. 322-323 [doi]
• Information optimization of distributed net of receivers of acoustic noise type signalsH. H. Asadov, N. A. Abdullayev, E. A. Ibrahimov, V. M. Garayev, E. Abbaszadeh. 324-325 [doi]
• Optimization of information - Measuring systems of non-stationary operational regime in multiple measurements modeH. H. Asadov, N. A. Abdullayev, I. K. Agayev, N. A. Nabiyev, R. T. Rajabli. 326-327 [doi]
• On possibility of stabilizing results for multicriteria optimizing linear combination of concurrent functionalsH. H. Asadov, N. A. Abdullayev, S. B. Jalilov, N. A. Nabiyev, N. H. Javadov. 328-329 [doi]
• FREP: A soft error resilient pipelined RISC architectureViney Kumar, Rahul Raj Choudhary, Virendra Singh. 330-333 [doi]
• Testing beyond the SoCs in a lego styleAnton Tsertov, Artur Jutman, Sergei Devadze. 334-338 [doi]
• Cluster computing framework based on transparent parallelizing technologyVitalij Pavlenko, Viktor Burdeinyi. 339-342 [doi]
• Thermal aware test scheduling for stacked multi-chip-modulesN. S. Vinay, Indira Rawaty, Erik Larsson, M. S. Gaur, Virendra Singh. 343-349 [doi]
• Fault grading using Instruction-Execution graphK. R. Vinutha, Virendra Singh, Anzhela Matrosova, M. S. Gaur. 350-357 [doi]
• System remote control of the robotized complex - PegasDmitry Bagayev, Evsyakov Artem. 358-361 [doi]
• Internet applications testing automation through probabilistic-network programmingA. A. Bykau, I. I. Piletsky. 362-365 [doi]
• Methodology of algorithms synthesis of storage devices test diagnosingMudar Almadi, Diaa Moamar, Vladimir Ryabtsev. 366-370 [doi]
• Building of the logic network of the information area of the corporationNina Khairova, Natalia Sharonova. 371-373 [doi]
• Development of the data-driven readout ASIC for microstrip detectorsEduard Atkin, Yuri Volkov, Alexander Klyuev, Vitaly Shumihin. 374-375 [doi]
• Advanced modeling of faults in Reversible circuitsIlia Polian, John P. Hayes. 376-381 [doi]
• Use of predicate categories for modelling of operation of the semantic analyzer of the linguistic processorNina Khairova, Natalia Sharonova. 382-385 [doi]
• Increase in reliability of on-line testing methods using natural time redundancyAlexander Drozd, Svetlana Antoshchuk, A. Martinuk, J. Drozd. 386-391 [doi]
• Reduction in the number of PAL macrocells for Moore FSM implemented with CPLDAlexander Barkalov, Larysa Titarenko, Slawomir Chmielewski. 390-394 [doi]
• ESL design methodology for architecture explorationFatemeh Javaheri, Zainalabedin Navabi. 395-401 [doi]
• A TLM2.0 assertion library with centralized monitoring approachAmirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi. 402-406 [doi]
• Schematic protection method from influence of total ionization dose effects on threshold voltage of MOS transistorsVazgen Melikyan, Aristakes Hovsepyan, Tigran Harutyunyan. 407-409 [doi]
• Virtual tester development using HDL/PLIArezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi. 412-415 [doi]
• Merit based directed random test generation (MDRTG) scheme for combinational circuitsArezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi. 416-419 [doi]
• Near optimal machine learning based random test generationNiki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi. 420-424 [doi]
• Security risks in hardware: Implementation and detection problemAlexander Adamov, Vladimir Hahanov. 425-427 [doi]
• Facilitating testability of TLM FIFO: SystemC implementationsHoma Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi. 428-431 [doi]
• Code optimization for enhancing SystemC simulation timeHoma Alemzadeh, Soheil Aminzadeh, Reihaneh Saberi, Zainalabedin Navabi. 431-434 [doi]
• 5V tolerant power clamps for mixed-voltage IC's in 65nm 2.5V salicided CMOS technologyVazgen Melikyan, Karen Sahakyan, Armen Nazaryan. 434-437 [doi]
• Hardware description language based on message passing and implicit pipeliningDmitri Boulytchev, Oleg Medvedev. 438-441 [doi]
• Between standard cells and transistors: Layout templates for Regular FabricsMikhail Talalay, Konstantin Trushin, Oleg Venger. 442-448 [doi]
• The problem of Trojan inclusions in software and hardwareAlexander Adamov, Alexander Saprykin. 449-451 [doi]
• Parameterized IP Infrastructures for fault-tolerant FPGA-based systems: Development, assessment, case-studyVitaliy Kulanov, Vyacheslav S. Kharchenko, Artem Perepelitsyn. 452-455 [doi]
• Generating test patterns for sequential circuits using random patterns by PLI functionsMohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi. 456-461 [doi]
• Low cost error tolerant motion estimation for H.264/AVC standardM. H. Sargolzaie, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi. 461-465 [doi]
• Method of diagnosing FPGA with use of geometrical imagesA. S. Epifanov. 465-468 [doi]
• System in Package. Diagnosis and embedded repairVladimir Hahanov, Aleksey Sushanov, Yulia Stepanova, Alexander Gorobets. 468-472 [doi]
• Technology for faulty blocks coverage by sparesVladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova, Oleg Zakharchenko, Natalya Kulbakova. 473-478 [doi]
• The Unicast Feedback models for real-time control protocolA. V. Babich, Murad Ali Abbas. 479-481 [doi]
• Algebra-logical repair method for FPGA logic blocksVladimir Hahanov, Sergey Galagan, Vitaliy Olchovoy, Aleksey Priymak. 482-487 [doi]
• Constructing test sequences for hardware designs with parallel starting operations using implicit FSM modelsMikhail M. Chupilko. 487-490 [doi]
• Redundant Multi-Level one-hot Residue Number System based error correction codesSomayyeh Jafarali Jassbi, Mehdi Hosseinzade, Keivan Navi. 491-494 [doi]
• IEEE 1500 compliant test wrapper generation tool for VHDL modelsSergey Mikhtonyuk, Maksim Davydov, Roman Hwang, Dmitry Shcherbin. 495-499 [doi]
• Early detection of potentially non-synchronized CDC paths using structural analysis techniqueDmitry Melnik, Olga Lukashenko, Sergey Zaychenko. 500-503 [doi]
• Architecture design and technical methodology for bus testingM. H. Haghbayan, Zainalabedin Navabi. 504-509 [doi]
• Assertion based verification in TLMAmirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi. 509-513 [doi]
• Advanced topics of FSM design using FPGA educational boards and web-based toolsAlexander Sudnitson, Dmitri Mihhailov, Margus Kruus. 514-517 [doi]
• A mixed HDL/PLI test packageNastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi. 518-523 [doi]
• n+1-1}Muhammad Mehdi Lotfinejad, Mohammad Mosleh, Hamid Noori. 524-526 [doi]
• Phase pictures of properties of complex objects of technical diagnosticsV. A. Tverdokhlebov. 527-530 [doi]
• Extended complete switch as ideal system networkMikhail F. Karavay, Victor S. Podlazov. 530-534 [doi]
• Image compression: Comparative analysis of basic algorithmsYevgeniya Sulema, Samira Ebrahimi Kahou. 534-537 [doi]
• Networked VLSI and MEMS designer for GridA. I. Petrenko. 538-544 [doi]
• COMPAS - Advanced test compressorJiri Jenícek, Ondrej Novák. 543-548 [doi]