Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. An Enhanced Path Delay Fault Simulator for Combinational Circuits. In 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland. pages 375-381, IEEE, 2011. [doi]
Abstract is missing.