Table of Contents

• Design challenges in 45nm and below: DFM, low-power and design for reliabilityPhilippe Magarshack. 1 [doi]
• Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-pathMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. 2-7 [doi]
• An optimized linear skewing interleave scheme for on-chip multi-access memory systemsChunyue Liu, Xiaolang Yan, Xing Qin. 8-13 [doi]
• I-cache multi-banking and vertical interleavingSangyeun Cho. 14-19 [doi]
• A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avcShen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto. 20-24 [doi]
• NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuitsDebasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack. 25-30 [doi]
• Dummy fill aware buffer insertion during routingYanming Jia, Yici Cai, Xianlong Hong. 31-36 [doi]
• Probabilistic gate-level power estimation using a novel waveform set methodSaeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas. 37-42 [doi]
• Robust wiring networks for DfY considering timing constraintsPhilipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl. 43-48 [doi]
• Simultaneous reduction in test data volume and test time for TRC-reseedingBin Zhou, Yizheng Ye, Yong-sheng Wang. 49-54 [doi]
• SEU mitigation for sram-based fpgas through dynamic partial reconfigurationCristiana Bolchini, Davide Quarta, Marco D. Santambrogio. 55-60 [doi]
• Estimating path delay distribution considering coupling noiseRajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham. 61-66 [doi]
• Co-evolutionary high-level test synthesisSoheil Aminzadeh, Saeed Safari. 67-72 [doi]
• Optimizing finfet technology for high-speed and low-power designTarun Sairam, Wei Zhao, Yu Cao. 73-77 [doi]
• Analysis of data dependence of leakage current in CMOS cryptographic hardwareJacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti. 78-83 [doi]
• Temperature-aware circuit design using adaptive body biasingYan Zhang, Mircea R. Stan. 84-89 [doi]
• A buffered crossbar-based chip interconnection framework supporting quality of serviceIoannis Papaefstathiou, George Kornaros, Nikolaos Chrysos. 90-95 [doi]
• Exact sat-based toffoli network synthesisDaniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler. 96-101 [doi]
• Combinational equivalence checking for threshold logic circuitsTejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod. 102-107 [doi]
• On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device resultsNadine Gergel-Hackett, Garrett S. Rose, Peter C. Paliwoda, Christina A. Hacker, Curt A. Richter. 108-113 [doi]
• Operation limits in RTD-based ternary quantizersJuan Núñez, José M. Quintana, Maria J. Avedillo. 114-119 [doi]
• Transition-activity aware design of reduction-stages for parallel multipliersSaeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson. 120-125 [doi]
• Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcastsChun-Mok Chung, Jihong Kim, Dohyung Kim. 126-131 [doi]
• GALS SoC interconnect bus for wireless sensor network processor platformsCarlos Fernández, Rajkumar K. Raval, Chris J. Bleakley. 132-137 [doi]
• Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessorsA. Robinson, Jim D. Garside. 138-143 [doi]
• Side-channel resistant system-level design flow for public-key cryptographyKazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede. 144-147 [doi]
• Area efficient loop filter design for charge pump phase locked loopR. G. Raghavendra, Bharadwaj Amrutur. 148-151 [doi]
• A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDSDariusz Kania. 152-155 [doi]
• A novel charge recycler for TFT-LCD source driver ICDan Li, Tingcun Wei, Wei Wu. 156-159 [doi]
• Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVCZhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga. 160-163 [doi]
• Compiler assisted architectural exploration for coarse grained reconfigurable arraysGrigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis. 164-167 [doi]
• Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imagingLinga Reddy Cenkeramaddi, Tajeshwar Singh, Trond Ytterdal. 168-171 [doi]
• RT level reliability enhancement by constructing dynamic TMRSNaghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi. 172-175 [doi]
• An asynchronous fpga logic cell implementationAtabak Mahram, Mehrdad Najibi, Hossein Pedram. 176-179 [doi]
• Real-time implementation of a time-frequency analysis schemeMaurizio Martina, Andrea Terreno, Fabrizio Vacca, Andrea Molino, Guido Masera, Giuseppe D Angelo, Giorgio Pasquettaz. 180-183 [doi]
• Flexible blocks for high throughput serially concatenated convolutional codesMaurizio Martina, Guido Masera. 184-187 [doi]
• Novel architectures for efficient (m, n) parallel countersSreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas. 188-191 [doi]
• High CMRR current mode operational amplifier with a novel class AB input stageMustafa Altun, Hakan Kuntman. 192-195 [doi]
• Hardware architecture for matrix factorization in mimo receiversBarbara Cerato, Guido Masera, Peter Nilsson. 196-199 [doi]
• Reduced-complexity mimo detector with close-to ml error rate performanceC. Hess, Markus Wenk, Andreas Burg, Peter Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner. 200-203 [doi]
• Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect densityMilos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani. 204-207 [doi]
• Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logicDrew C. Ness, Christian J. Hescott, David J. Lilja. 208-211 [doi]
• A symmetric mos current-mode logic universal gate for high speed applicationsOsman Musa Abdulkarim, Maitham Shams. 212-215 [doi]
• An automated unique tagging system using CMOS process variationBrandon L. Dell, Jonathan F. Bolus, Travis N. Blalock. 216-218 [doi]
• A design kit for a fully working shared memory multiprocessor on FPGAAntonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 219-222 [doi]
• Probabilistic maximum error modeling for unreliable logic circuitsKarthikeyan Lingasubramanian, Sanjukta Bhanja. 223-226 [doi]
• Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technologyRiaz Naseer, Jeff Draper, Younes Boulghassoul, Sandeepan DasGupta, Art Witulski. 227-230 [doi]
• Active bank switching for temperature control of the register file in a microprocessorKimish Patel, Wonbok Lee, Massoud Pedram. 231-234 [doi]
• Sleep transistor distribution in row-based MTCMOS designsChanseok Hwang, Peng Rong, Massoud Pedram. 235-240 [doi]
• A new decompression system for the configuration process of SRAM-based FPGASLuca Sterpone, Massimo Violante. 241-246 [doi]
• Minimizing peak power in synchronous logic circuitsKambiz Rahimi. 247-252 [doi]
• Linearized CMOS active resistor independent on the bulk effectCosmin Popa. 253-256 [doi]
• Structured and tuned array generation (STAG) for high-performance random logicMatthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan. 257-262 [doi]
• Design of mixed gates for leakage reductionFrank Sill, Jiaixi You, Dirk Timmermann. 263-268 [doi]
• Modeling and estimating leakage current in series-parallel CMOS networksPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas. 269-274 [doi]
• Analyzing and modeling process balance for sub-threshold circuit designJoseph F. Ryan, Jiajing Wang, Benton H. Calhoun. 275-280 [doi]
• Viewing direction-aware backlight scalingChih-Nan Wu, Wei-Chung Cheng. 281-286 [doi]
• Synthesis of irregular combinational functions with large don t care setsValentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers. 287-292 [doi]
• DAG based library-free technology mappingFelipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. 293-298 [doi]
• Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraintMehrdad Najibi, Kamran Saleh, Hossein Pedram. 299-304 [doi]
• An evolutionary approach for standard-cell library reductionAndrea Ricci, Ilaria De Munari, Paolo Ciampolini. 305-310 [doi]
• Multi-processor operating system emulation framework with thermal feedback for systems-on-chipSalvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias. 311-316 [doi]
• Computer-aided design of 3d integrated circuitsSachin S. Sapatnekar. 317 [doi]
• DFM issues for 65nm and beyondJamil Kawa, Charles Chiang. 318-322 [doi]
• Utilizing custom registers in application-specific instruction set processors for register spills eliminationHai Lin, Yunsi Fei. 323-328 [doi]
• Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodologyNaser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi. 329-334 [doi]
• Beyond 3G wireless communication system prototypeAlberto Dassatti, Simone Zezza, Mario Nicola, Guido Masera. 335-340 [doi]
• A new hardware architecture for performing the gridding of DNA microarray imagesLuca Sterpone, Massimo Violante. 341-346 [doi]
• A design methodology for space-time adapterCyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. 347-352 [doi]
• A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loopsTarvo Raudvere, Ingo Sander, Axel Jantsch. 353-358 [doi]
• HW/SW partitioning using discrete particle swarmAmin Farmahini Farahani, Mehdi Kamal, Seid Mehdi Fakhraie, Saeed Safari. 359-364 [doi]
• Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesisYuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii. 365-370 [doi]
• Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnectsChittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas. 371-376 [doi]
• A 5 GHz wide band input and output matched low noise amplifierRoghoyeh Salmeh, Brent Maundy. 377-380 [doi]
• A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmissionHimanshu Arora, Nikolaus Klemmer, Patrick Wolf. 381-386 [doi]
• Design of an UHF RFID transponder for secure authenticationPaolo Bernardi, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez. 387-392 [doi]
• Effective heuristics for counterexample-guided abstraction refinementFei He, Xiaoyu Song, Ming Gu, Jiaguang Sun. 393-398 [doi]
• Reducing verification overhead with RTL slicingJen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham. 399-404 [doi]
• Optimization techniques for BDD-based bisimulation computationRalf Wimmer, Marc Herbstritt, Bernd Becker. 405-410 [doi]
• Hardware-accelerated path-delay fault grading of functional test programs for processor-based systemsPaolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda. 411-416 [doi]
• An approximation algorithm for fully testable kEP-SOP networksAnna Bernasconi, Valentina Ciriani, Roberto Cordone. 417-422 [doi]
• A coefficient optimization and architecture selection tool for SD modulators considering component non-idealitiesOrkun Saglamdemir, Ömer Yetik, Selçuk Talay, Günhan Dündar. 423-428 [doi]
• Hand-in-hand verification of high-level synthesisChandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade. 429-434 [doi]
• Area minimization algorithm for parallel prefix adders under bitwise delay constraintsTaeko Matsunaga, Yusuke Matsunaga. 435-440 [doi]
• A new algorithm for the largest compositionally progressive solution of synchronous language equationsTiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 441-444 [doi]
• An efficient cost-based canonical form for Boolean matchingGiovanni Agosta, Francesco Bruschi, Donatella Sciuto. 445-448 [doi]
• Evaluation of using active circuitry for substrate noise suppressionRashid Farivar, Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson. 449-452 [doi]
• The effect of temperature on cache size tuning for low energy embedded systemsHamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami. 453-456 [doi]
• Efficient space-time noc path allocation based on mutual exclusion and pre-reservationSamuel Evain, Jean-Philippe Diguet. 457-460 [doi]
• Skew spreading for peak current reductionZhentao Yu, Marios C. Papaefthymiou, Xun Liu. 461-464 [doi]
• Block placement to ensure channel routabilityShigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh. 465-468 [doi]
• GA-SVM feasibility model and optimization kernel applied to analog IC design automationManuel Barros, Jorge Guilherme, Nuno Horta. 469-472 [doi]
• Physical aware clock skew reschedulingXinjie Wei, Yici Cai, Xianlong Hong. 473-476 [doi]
• A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershootsRachit Kumar Gupta, Vikas Narang, H. M. Roopashree, Vinod Menezes. 477-480 [doi]
• Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapathKoji Ohashi, Mineo Kaneko. 481-484 [doi]
• Three-valued automated reasoning on analog propertiesRaffaella Gentilini, Klaus Schneider, Alexander Dreyer. 485-488 [doi]
• On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessorsOlga Golubeva, Mirko Loghi, Massimo Poncino. 489-492 [doi]
• Improvements for constraint solving in the systemc verification libraryDaniel Große, Rüdiger Ebendt, Rolf Drechsler. 493-496 [doi]
• Systematic design of two-stage operational amplifiers based on settling time and open-loop constraintsHamed Aminzadeh, Mohammad Danaie. 497-500 [doi]
• Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technologyAndrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 501-504 [doi]
• StateCharts to systemc: a high level hardware simulation approachMarcello Mura, Marco Paolieri, Luca Negri, Mariagiovanna Sami. 505-508 [doi]
• A lightweight parallel java execution environment for embedded multiprocessor systems-on-chipMarco Mantovani, Simone Leardini, Martino Ruggiero, Andrea Acquaviva, Luca Benini. 509-512 [doi]
• Improvement of power distribution network using correlation-based regression analysisShiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu. 513-516 [doi]
• A high-level register optimization technique for minimizing leakage and dynamic powerDeniz Dal, Nazanin Mansouri. 517-520 [doi]
• An efficient net ordering algorithm for buffer insertionHamid Reza Kheirabadi, Morteza Saheb Zamani. 521-524 [doi]
• Address generation for nanowire decodersJia Wang, Ming-Yang Kao, Hai Zhou. 525-528 [doi]
• Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designersKiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara. 529-533 [doi]
• Efficient pipelining for modular multiplication architectures in prime fieldsNele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede. 534-539 [doi]
• Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processorChichyang Chen, Paul Chow. 540-545 [doi]
• Multi-segment ::::GF::::(2:::::::m:::::::) multiplication and its application to elliptic curve cryptographyDong-Ho Lee, Jong-Soo Oh. 546-551 [doi]
• Floorplan repair using dynamic whitespace managementKristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat. 552-557 [doi]
• Improved timing closure by early buffer planning in floor-placement design flowAli Jahanian, Morteza Saheb Zamani. 558-563 [doi]
• An effective buffer planning algorithm for IP based fixed-outline SOC placementOu He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong. 564-569 [doi]
• New timing and routability driven placement algorithms for FPGA synthesisYue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong. 570-575 [doi]
• RT-level vector selection for realistic peak power simulationChia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang. 576-581 [doi]
• A fast clock scheduling for peak power reduction in LSIYosuke Takahashi, Yukihide Kohira, Atsushi Takahashi. 582-587 [doi]
• A path based modeling approach for dynamic power estimationPrashant Agrawal, R. Srinivasa, Ajit N. Oke, Saurabh Vijay. 588-593 [doi]
• Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processorKyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung. 594-599 [doi]
• Future trends for wireless communication frontends in nanometer CMOSGeorges G. E. Gielen. 600-605 [doi]