Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas. Novel architectures for efficient (m, n) parallel counters. In Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud, editors, Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007. pages 188-191, ACM, 2007. [doi]
Abstract is missing.