Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas. Novel architectures for efficient (m, n) parallel counters. In Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud, editors, Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007. pages 188-191, ACM, 2007. [doi]
@inproceedings{VeeramachaneniAKS07,
title = {Novel architectures for efficient (m, n) parallel counters},
author = {Sreehari Veeramachaneni and Lingamneni Avinash and Kirthi M. Krishna and M. B. Srinivas},
year = {2007},
doi = {10.1145/1228784.1228833},
url = {http://doi.acm.org/10.1145/1228784.1228833},
tags = {architecture},
researchr = {https://researchr.org/publication/VeeramachaneniAKS07},
cites = {0},
citedby = {0},
pages = {188-191},
booktitle = {Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007},
editor = {Hai Zhou and Enrico Macii and Zhiyuan Yan and Yehia Massoud},
publisher = {ACM},
isbn = {978-1-59593-605-9},
}