Matthew M. Ziegler - researchr alias

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Viewing Publication 1 - 47 from 47

2024

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoCMonodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan 0001, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang 0333, Vidhi Zalani, Jintao Zhang, Xin Zhang 0025, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang. isscc 2024: 254-256 [doi]

2022

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware ThrottlingSae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang 0333, Xin Zhang 0025, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang. jssc, 57(1):182-197, 2022. [doi]

Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic TuningMatthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch. ispd 2022: 29-37 [doi]

2021

RaPiD: AI Accelerator for Ultra-low Precision Training and InferenceSwagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan. isca 2021: 153-166 [doi]

Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper)Matthew M. Ziegler, Jihye Kwon, Hung-Yi Liu, Luca P. Carloni. iccad 2021: 1-9 [doi]

2020

2019

Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED)Andreas Burg, Matthew M. Ziegler, Saibal Mukhopdhyay. dt, 36(6):82-83, 2019. [doi]

Resilient Low Voltage Accelerators for High Energy EfficiencyNandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri, Schuyler Eldridge, Rajiv V. Joshi, Matthew M. Ziegler, Alper Buyuktosunoglu, Pradip Bose. hpca 2019: 147-158 [doi]

Low Power Design From Moore to AI for nm Era : Invited PaperRajiv V. Joshi, Matthew M. Ziegler. mixdes 2019: 59-64 [doi]

A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance ProcessorsJihye Kwon, Matthew M. Ziegler, Luca P. Carloni. dac 2019: 218 [doi]

Research From the IEEE IBM AI Compute and Emerging Technology SymposiaMatthew M. Ziegler, Krishnan Kailas, Xin Zhang, Rajiv V. Joshi. esticas, 9(3):435-438, 2019. [doi]

2018

Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applicationsRajiv V. Joshi, Matthew M. Ziegler, Karthik Swaminathan, Nandhini Chandramoorthy. cicc 2018: 1-4 [doi]

2017

A Low Voltage SRAM Using Resonant Supply BoostingRajiv V. Joshi, Matthew M. Ziegler, Holger Wetter. jssc, 52(3):634-644, 2017. [doi]

Programmable supply boosting techniques for near threshold and wide operating voltage SRAMRajiv V. Joshi, Matthew M. Ziegler. cicc 2017: 1-4 [doi]

Machine learning techniques for taming the complexity of modern hardware designMatthew M. Ziegler, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose. ibmrd, 61(4):13, 2017. [doi]

2016

2015

Super Fast Physics-Based Methodology for Accurate Memory Yield PredictionRajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh. tvlsi, 23(3):534-543, 2015. [doi]

14nm FinFET based supply voltage boosting techniques for extreme low Vmin operationRajiv V. Joshi, Matthew M. Ziegler, H. Wetter, C. Wandel, Herschel A. Ainspan. vlsic 2015: 268 [doi]

2014

Bridging high performance and low power in processor designRuchir Puri, Mihir R. Choudhury, Haifeng Qian, Matthew M. Ziegler. islped 2014: 183-188 [doi]

POWER8 design methodology innovations for improving productivity and reducing powerMatthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert Franch, Wing Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban. cicc 2014: 1-9 [doi]

2013

2009

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija. patmos 2010: 307-316 [doi]

The opportunity cost of low power design: a case study in circuit tuningMatthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich. islped 2009: 133-138 [doi]

2008

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell BiasingAzeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler. jssc, 43(4):946-955, 2008. [doi]

2007

Multi-Dimensional Circuit and Micro-Architecture Level OptimizationZhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan. isqed 2007: 275-280 [doi]

Structured and tuned array generation (STAG) for high-performance random logicMatthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan. glvlsi 2007: 257-262 [doi]

2006

Hybrid CMOS/Molecular Electronic CircuitsMircea R. Stan, Garrett S. Rose, Matthew M. Ziegler. vlsid 2006: 703-708 [doi]

2004

Large-signal two-terminal device model for nanoelectronic circuit analysisGarrett S. Rose, Matthew M. Ziegler, Mircea R. Stan. tvlsi, 12(11):1201-1208, 2004. [doi]

A Unified Design Space for Regular Parallel Prefix AddersMatthew M. Ziegler, Mircea R. Stan. date 2004: 1386-1387 [doi]

2003

Molecular electronics: from devices and interconnect to circuits and architectureMircea R. Stan, Paul D. Franzon, Seth Copen Goldstein, John C. Lach, Matthew M. Ziegler. pieee, 91(11):1940-1957, 2003. [doi]

The CMOS/nano interface from a circuits perspectiveMatthew M. Ziegler, Mircea R. Stan. iscas 2003: 904-907 [doi]

2002

A Case for CMOS/nano co-designMatthew M. Ziegler, Mircea R. Stan. iccad 2002: 348-352 [doi]

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Publications by 'Matthew M. Ziegler'

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