James D. Warnock - researchr alias

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Viewing Publication 1 - 31 from 31

2018

Impact of Device Aging on Early Mode Failures in Pulsed LatchesAnkur Shukla, Rahul M. Rao, James D. Warnock. vlsid 2018: 256-260 [doi]

2016

Design-synthesis co-optimisation using skewed and tapered gatesAyan Datta, James D. Warnock, Ankur Shukla, Saurabh Gupta, Yiu H. Chan, Karthik Mohan, Charudhattan Nagarajan. date 2016: 1144-1147 [doi]

2015

A case study of electromigration reliability: From design point to system operationsBaozhen Li, K. Paul Muller, James D. Warnock, Leon J. Sigal, Dinesh Badami. irps 2015: 2 [doi]

2014

2013

2012

2011

Design, CAD and technology challenges for future processors: 3D perspectivesJeff Burns, Gary Carpenter, Eren Kursun, Ruchir Puri, James D. Warnock, Michael Scheuermann. dac 2011: 212 [doi]

The zEnterprise 196 System and MicroprocessorBrian W. Curran, Lee Eisen, Eric M. Schwarz, Pak-kin Mak, James D. Warnock, Patrick J. Meaney, Michael F. Fee. micro, 31(2):26-40, 2011. [doi]

Circuit design challenges at the 14nm technology nodeJames D. Warnock. dac 2011: 464-467 [doi]

2010

TM local clocking and clocked storage elementsJames D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski. isscc 2010: 178-179 [doi]

2007

Cell Broadband Engine processor: Design and implementationMack W. Riley, James D. Warnock, Dieter F. Wendel. ibmrd, 51(5):545-558, 2007. [doi]

Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits ConferenceJames D. Warnock, William Bidermann, Albert van der Werf, Katsuyuki Sato. jssc, 42(1):3-6, 2007. [doi]

2006

Circuit Design Techniques for a First-Generation Cell Broadband Engine ProcessorJames D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen. jssc, 41(8):1692-1706, 2006. [doi]

2005

2002

The circuit and physical design of the POWER4 microprocessorJames D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip Restle, Brian A. Zoric, Carl J. Anderson. ibmrd, 46(1):27-52, 2002. [doi]

1997

Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessorLeon J. Sigal, James D. Warnock, Brian W. Curran, Yuen H. Chan, Peter J. Camporese, Mark D. Mayo, William V. Huott, Daniel R. Knebel, Ching-Te Chuang, James P. Eckhardt, Philip T. Wu. ibmrd, 41(4&5):489-504, 1997. [doi]

High-Performance CMOS Circuit Techniques for the G-4 S/390 MicroprocessorJames D. Warnock, Leon J. Sigal, Brian W. Curran, Yuen H. Chan. iccd 1997: 247-252

1995

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applicationsG. G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, J. Y.-C. Sun, Michael R. Polcari, Bijan Davari. ibmrd, 39(1-2):229-244, 1995.

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