Abstract is missing.
- Challenging device innovationSatoru Ito. [doi]
- Effective platform-based development for large-scale systems designYukichi Niwa. [doi]
- Automotive electronics: steady growth for years to come!Alberto L. Sangiovanni-Vincentelli. [doi]
- Transition-based coverage estimation for symbolic model checkingXingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya. 1-6 [doi]
- Word level functional coverage computationBijan Alizadeh. 7-12 [doi]
- Discovering the input assumptions in specification refinement coveragePrasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti. 13-18 [doi]
- Refinement strategies for verification methods based on datapath abstractionZaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah. 19-24 [doi]
- Generation of shorter sequences for high resolution error diagnosis using sequential SATSung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna. 25-29 [doi]
- Constraint-driven bus matrix synthesis for MPSoCSudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane. 30-35 [doi]
- Improving routing efficiency for network-on-chip through contention-aware input selectionDong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz. 36-41 [doi]
- Physical design implementation of segmented buses to reduce communication energyJin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor. 42-47 [doi]
- Co-synthesis of a configurable SoC platform based on a network on chip architectureMário P. Véstias, Horácio C. Neto. 48-53 [doi]
- Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorizationMuhammad Omer Cheema, Omar Hammami. 54-60 [doi]
- Robust analytical gate delay modeling for low voltage circuitsAnand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan. 61-66 [doi]
- CGTA: current gain-based timing analysis for logic cellsShahin Nazarian, Massoud Pedram, Tao Lin, Emre Tuncer. 67-72 [doi]
- Efficient static timing analysis using a unified framework for false paths and multi-cycle pathsShuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton. 73-78 [doi]
- Crosstalk analysis using reconvergence correlationSachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma. 79-83 [doi]
- Process-induced skew reduction in nominal zero-skew clock treesMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown. 84-89 [doi]
- A low dynamic power and low leakage power 90-nm CMOS square-root circuitTadayoshi Enomoto, Nobuaki Kobayashi. 90-91 [doi]
- A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuitsLili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi. 92-93 [doi]
- A 16-bit, low-power microsystem with monolithic MEMS-::::LC:::: clockingRobert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown. 94-95 [doi]
- Ultra-low voltage power management circuit and computation methodology for energy harvesting applicationsChi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su. 96-97 [doi]
- A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppressionKoichi Ishida, Atit Tamtrakarn, Takayasu Sakurai. 98-99 [doi]
- An implementation of a CMOS down-conversion mixer for GSM1900 receiverFangqing Chu, Wei Li, Junyan Ren. 100-101 [doi]
- Integrated direct output current control switching converter using symmetrically-matched self-biased current sensorsYat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui. 102-103 [doi]
- Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedbackYat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui. 104-105 [doi]
- A built-in power supply noise probe for digital LSIsMitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki. 106-107 [doi]
- A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technologyMinoru Watanabe, Fuminori Kobayashi. 108-109 [doi]
- Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devicesKazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera. 110-111 [doi]
- High-throughput decoder for low-density parity-check codeTatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto. 112-113 [doi]
- Hardware implementation of super minimum all digital FM demodulatorNursani Rahmatullah, Arif E. Nugroho. 114-115 [doi]
- Designing a custom architecture for DCT using NISC technologyBita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski. 116-117 [doi]
- A 52mW 1200MIPS compact DSP for multi-core media SoCShih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen. 118-119 [doi]
- Implementation of H.264/AVC decoder for mobile video applicationsSuh Ho Lee, Ji-Hwan Park, Seon Wook Kim, Sung Jea Ko, Suki Kim. 120-121 [doi]
- A high-performance platform-based SoC for information securityMin Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan. 122-123 [doi]
- Configurable multi-processor architecture and its processor element designTsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi. 124-125 [doi]
- Design and implementation of transducer for ARM-TMS communicationHansu Cho, Samar Abdi, Daniel Gajski. 126-127 [doi]
- Energy savings through embedded processing on disk systemSeung Woo Son, Guangyu Chen, Mahmut T. Kandemir, Feihui Li. 128-133 [doi]
- Energy-aware computation duplication for improving reliability in embedded chip multiprocessorsGuilin Chen, Mahmut T. Kandemir, Feihui Li. 134-139 [doi]
- Object duplication for improving reliabilityGuilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. 140-145 [doi]
- Mapping and configuration methods for multi-use-case networks on chipsSrinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli. 146-151 [doi]
- Conversion of reference C code to dataflow model: H.264 encoder case studyHyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi Ha. 152-157 [doi]
- SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor designHai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh. 158-163 [doi]
- The design and implementation of a low-latency on-chip networkRobert D. Mullins, Andrew West, Simon W. Moore. 164-169 [doi]
- A near optimal deblocking filter for H.264 advanced video codingShen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin. 170-175 [doi]
- Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object trackingK. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch. 176-181 [doi]
- Prefetching-aware cache line turnoff for saving leakage energyIsmail Kadayif, Mahmut T. Kandemir, Feihui Li. 182-187 [doi]
- A robust detailed placement for mixed-size IC designsJason Cong, Min Xie. 188-194 [doi]
- FastPlace 2.0: an efficient analytical placer for mixed-mode designsNatarajan Viswanathan, Min Pan, Chris C. N. Chu. 195-200 [doi]
- Timing-driven placement based on monotone cell ordering constraintsChanseok Hwang, Massoud Pedram. 201-206 [doi]
- Constraint driven I/O planning and placement for chip-package co-designJinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He. 207-212 [doi]
- Simultaneous block and I/O buffer floorplanning for flip-chip designChih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang. 213-218 [doi]
- Electrothermal analysis and optimization techniques for nanoscale integrated circuitsYong Zhan, Brent Goplen, Sachin S. Sapatnekar. 219-222 [doi]
- Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systemsKaustav Banerjee, Sheng-Chih Lin, Navin Srivastava. 223-230 [doi]
- Area optimization for leakage reduction and thermal stability in nanometer scale technologiesJa Chun Ku, Yehea I. Ismail. 231-236 [doi]
- Compact thermal models for estimation of temperature-dependent power/performance in FinFET technologyAditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy. 237-242 [doi]
- An anytime symmetry detection algorithm for ROBDDsNeil Kettle, Andy King. 243-248 [doi]
- High level equivalence symmetric input identificationMing-Hong Su, Chun-Yao Wang. 249-253 [doi]
- Fast multi-domain clock skew scheduling for peak current reductionShih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh. 254-259 [doi]
- Low area pipelined circuits by multi-clock cycle paths and clock schedulingBakhtiar Affendi Rosdi, Atsushi Takahashi. 260-265 [doi]
- A transduction-based framework to synthesize RSFQ circuitsShigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi. 266-272 [doi]
- Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomenaXiaolue Lai, Jaijeet S. Roychowdhury. 273-278 [doi]
- ::::Newton::::: a library-based analytical synthesis tool for RF-MEMS resonatorsMichael S. McCorquodale, James L. McCann, Richard B. Brown. 279-284 [doi]
- Jitter decomposition in ring oscillatorsQingqi Dou, Jacob A. Abraham. 285-290 [doi]
- A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodelsPrashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury. 291-296 [doi]
- Double edge triggered Feedback Flip-Flop in sub 100NM technologyS. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha. 297-302 [doi]
- Post-routing redundant via insertion for yield/reliability improvementKuang-Yao Lee, Ting-Chi Wang. 303-308 [doi]
- Temperature-aware routing in 3D ICsTianpei Zhang, Yong Zhan, Sachin S. Sapatnekar. 309-314 [doi]
- Closed form solution for optimal buffer sizing using the Weierstrass elliptic functionSebastian Vogel, Martin D. F. Wong. 315-319 [doi]
- An ::::O::::(::::mn::::) time algorithm for optimal buffer insertion of nets with ::::m:::: sinksZhuo Li, Weiping Shi. 320-325 [doi]
- Spec-based flip-flop and latch repeater planningMan Chung Hon. 326-331 [doi]
- Current trends in flash memory technology: invited paperSang Lyul Min, Eyee Hyun Nam. 332-333 [doi]
- Configurability of performance and overheads in flash managementTei-Wei Kuo, Jen-Wei Hsieh, Li-Pin Chang, Yuan-Hao Chang. 334-341 [doi]
- Delay defect screening for a 2.16GHz SPARC64 microprocessorNoriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi. 342-347 [doi]
- A dynamic test compaction procedure for high-quality path delay testingMasayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato. 348-353 [doi]
- Delay variation tolerance for domino circuitsKai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang. 354-359 [doi]
- Efficient identification of multi-cycle false pathKai Yang, Kwang-Ting Cheng. 360-365 [doi]
- IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faultsKatherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen. 366-371 [doi]
- High-level architecture exploration for MPEG4 encoder with custom parametersMarius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Youssef, Xi Chen, Wander O. Cesário, Ahmed Amine Jerraya. 372-377 [doi]
- Programmable numerical function generators based on quadratic approximation: architecture and synthesis methodShinobu Nagayama, Tsutomu Sasao, Jon T. Butler. 378-383 [doi]
- An automated design flow for 3D microarchitecture evaluationJason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang. 384-389 [doi]
- Optimal topology exploration for application-specific 3D architecturesOzcan Ozturk, Feng Wang 0004, Mahmut T. Kandemir, Yuan Xie. 390-395 [doi]
- Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systemsJesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos. 396-401 [doi]
- A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplingsZhao Li, C.-J. Richard Shi. 402-407 [doi]
- An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuitsKiyotaka Yamamura, Wataru Kuroki. 408-415 [doi]
- Optimization of circuit trajectories: an auxiliary network approachBaohua Wang, Pinaki Mazumder. 416-421 [doi]
- SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devicesJitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan. 422-427 [doi]
- An unconditional stable general operator splitting method for transistor level transient analysisZhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh. 428-433 [doi]
- An introduction to OpenAccess: an open source data model and API for IC designMichaela Guiney, Eric Leavitt. 434-436 [doi]
- Open access overview industrial experience Yoshio Inoue. 437-438 [doi]
- EDA vendor adoptionHillel Ofek. 439 [doi]
- Utility of the OpenAccess database in academic researchDavid A. Papa, Igor L. Markov, Philip Chong. 440-441 [doi]
- Depth-driven verification of simultaneous interfacesIlya Wagner, Valeria Bertacco, Todd M. Austin. 442-447 [doi]
- FSM-based transaction-level functional coverage for interface compliance verificationMan-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou. 448-453 [doi]
- Hardware debugging method based on signal transitions and transactionsNobuyuki Ohba, Kohji Takano. 454-459 [doi]
- Cycle error correction in asynchronous clock modeling for cycle-based simulationJungHee Lee, Joonhwan Yi. 460-465 [doi]
- A fast logic simulator using a look up table cascade emulatorHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura. 466-472 [doi]
- Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time systemPeng Rong, Massoud Pedram. 473-478 [doi]
- Optimal TDMA time slot and cycle length allocation for hard real-time systemsErnesto Wandeler, Lothar Thiele. 479-484 [doi]
- POSIX modeling in SystemCHector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco. 485-490 [doi]
- PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architecturesSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt. 491-496 [doi]
- Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphsHyunok Oh, Nikil Dutt, Soonhoi Ha. 497-502 [doi]
- Wire sizing with scattering effect for nanoscale interconnectionSean X. Shi, David Z. Pan. 503-508 [doi]
- Adaptive admittance-based conductor meshing for interconnect analysisYa-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan. 509-514 [doi]
- Interconnect RL extraction at a single representative frequencyAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera. 515-520 [doi]
- An efficient algorithm for 3-D reluctance extraction considering high frequency effectMengsheng Zhang, Wenjian Yu, Yu Du, Zeyi Wang. 521-526 [doi]
- Macromodelling oscillators using Krylov-subspace methodsXiaolue Lai, Jaijeet S. Roychowdhury. 527-532 [doi]
- Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systemsTakeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami. 533-540 [doi]
- Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noiseSatoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga. 541-546 [doi]
- A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulationMasafumi Onouchi, Tetsuya Yamada, Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine. 547-550 [doi]
- PowerV::::i::::P: Soc power estimation framework at transaction levelIkhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo. 551-558 [doi]
- Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systemsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. 559-564 [doi]
- Analysis and optimization of gate leakage current of power gating circuitsHyung-Ock Kim, Youngsoo Shin. 565-569 [doi]
- Delay modeling and static timing analysis for MTCMOS circuitsNaoaki Ohkubo, Kimiyoshi Usami. 570-575 [doi]
- Switching-activity driven gate sizing and Vth assignment for low power designYu-Hui Huang, Po-Yuan Chen, TingTing Hwang. 576-581 [doi]
- Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designsBin Liu, Yici Cai, Qiang Zhou, Xianlong Hong. 582-587 [doi]
- Reusable component IP design using refinement-based design environmentSanggyu Park, Sang-yong Yoon, Soo-Ik Chae. 588-593 [doi]
- An interface-circuit synthesis method with configurable processor core in IP-based SoC designsShunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 594-599 [doi]
- A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communicationChien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou. 600-605 [doi]
- Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applicationsQubo Hu, Arnout Vandecappelle, Martin Palkovic, Per Gunnar Kjeldsberg, Erik Brockmeyer, Francky Catthoor. 606-611 [doi]
- A novel instruction scratchpad memory optimization method based on concomitance metricAndhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran. 612-617 [doi]
- DraXRouter: global routing in X-Architecture with dynamic resource assignmentZhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan. 618-623 [doi]
- Diagonal routing in high performance microprocessor designNoriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama. 624-629 [doi]
- CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit modelYiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlong Hong. 630-635 [doi]
- A novel framework for multilevel full-chip gridless routingTai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin. 636-641 [doi]
- Monotonic parallel and orthogonal routing for single-layer ball grid array packagesYoichi Tomioka, Atsushi Takahashi. 642-647 [doi]
- A routability constrained scan chain ordering technique for test power reductionX.-L. Huang, J.-L. Huang. 648-652 [doi]
- FCSCAN: an efficient multiscan-based test compression technique for test cost reductionYouhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki. 653-658 [doi]
- Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuitsYoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu. 659-664 [doi]
- Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capabilityAshish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy. 665-670 [doi]
- A memory grouping method for sharing memory BIST logicMasahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara. 671-676 [doi]
- Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolationDaisuke Kosaka, Makoto Nagata. 677-682 [doi]
- A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profilesXiren Wang, Wenjian Yu, Zeyi Wang. 683-688 [doi]
- Parasitics extraction involving 3-D conductors based on multi-layered Green s functionZuochang Ye, Zhiping Yu. 689-693 [doi]
- Signal-path driven partition and placement for analog circuitDi Long, Xianlong Hong, Sheqin Dong. 694-699 [doi]
- An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysisXiaoying Wang, Lars Hedrich. 700-705 [doi]
- Statistical corner conditions of interconnect delay (corner LPE specifications)Kenta Yamada, Noriaki Oda. 706-711 [doi]
- Speed binning aware design methodology to improve profit under parameter variationsAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy. 712-717 [doi]
- Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)Vineet Agarwal, Janet Meiling Wang. 718-723 [doi]
- A probabilistic analysis of pipelined global interconnect under process variationsNavneeth Kankani, Vineet Agarwal, Janet Meiling Wang. 724-729 [doi]
- Yield-preferred via insertion based on novel geotopological technologyFangyi Luo, Yongbo Jia, Wayne Wei-Ming Dai. 730-735 [doi]
- Introduction to H.264 advanced video codingJian-Wen Chen, Chao-Yang Kao, Youn-Long Lin. 736-741 [doi]
- Algorithms and DSP implementation of H.264/AVCHung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang. 742-749 [doi]
- Hardware architecture design of an H.264/AVC video codecTung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen. 750-757 [doi]
- ASIP approach for implementation of H.264/AVCSung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung Hoon Sunwoo. 758-764 [doi]
- Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCsMinsik Cho, Hongjoong Shin, David Z. Pan. 765-770 [doi]
- A fixed-die floorplanning algorithm using an analytical approachYong Zhan, Yan Feng, Sachin S. Sapatnekar. 771-776 [doi]
- A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafersChien-Chang Chen, Wai-Kei Mak. 777-782 [doi]
- Design space exploration for minimizing multi-project wafer production costRung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai. 783-788 [doi]
- SAT-based optimal hypergraph partitioning with replicationMichael G. Wrighton, André DeHon. 789-795 [doi]
- Finding optimal L1 cache configuration for embedded systemsAndhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran. 796-801 [doi]
- Memory size computation for multimedia processing applicationsHongwei Zhu, Ilie I. Luican, Florin Balasa. 802-807 [doi]
- Maximizing data reuse for minimizing memory space requirements and execution cyclesMahmut T. Kandemir, Guangyu Chen, Feihui Li. 808-813 [doi]
- Compiler-Guided data compression for reducing memory consumption of embedded applicationsOzcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu. 814-819 [doi]
- Analysis of scratch-pad and data-cache performance using statistical methodsJaved Absar, Francky Catthoor. 820-825 [doi]
- Efficient early stage resonance estimation techniques for C4 packageJin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong. 826-831 [doi]
- Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parametersTakayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai. 832-837 [doi]
- Power distribution techniques for dual VDD circuitsSarvesh H. Kulkarni, Dennis Sylvester. 838-843 [doi]
- Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element methodChanghao Yan, Wenjian Yu, Zeyi Wang. 844-849 [doi]
- Controlling inductive cross-talk and power in off-chip buses using CODECsBrock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri. 850-855 [doi]
- A new test and characterization scheme for 10+ GHz low jitter wide band PLLKazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto. 856-859 [doi]
- An SPU reference model for simulation, random test generation and verificationYukio Watanabe, Balazs Sallay, Brad W. Michael, Daniel A. Brokenshire, Gavin Meil, Hazim Shafi, Daisuke Hiraoka. 860-866 [doi]
- A cycle accurate power estimation toolRajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong. 867-870 [doi]
- Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processorDac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel. 871-878 [doi]
- TAPHS: thermal-aware unified physical-level and high-level synthesisZhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert P. Dick, Li Shang. 879-885 [doi]
- An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic modelYu Pu, Yajun Ha. 886-891 [doi]
- Abridged addressing: a low power memory addressing strategyPreeti Ranjan Panda. 892-897 [doi]
- Using speculative computation and parallelizing techniques to improve scheduling of control based designsRoberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto. 898-904 [doi]
- Worst case execution time analysis for synthesized hardwareJun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi. 905-910 [doi]
- Workload prediction and dynamic voltage scaling for MPEG decodingYing Tan, Parth Malani, Qinru Qiu, Qing Wu. 911-916 [doi]
- Lazy BTB: reduce BTB energy consumption using dynamic profilingYen-Jen Chang. 917-922 [doi]
- Cache size selection for performance, energy and reliability of time-constrained systemsYuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy. 923-928 [doi]
- Reducing dynamic compilation overhead by overlapping compilation and executionPriya Unnikrishnan, Mahmut T. Kandemir, Feihui Li. 929-934 [doi]
- Functional modeling techniques for efficient SW code generation of video codec applicationsSang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya. 935-940 [doi]
- Convergence-provable statistical timing analysis with level-sensitive latches and feedback loopsLizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen. 941-946 [doi]
- Parameterized block-based non-gaussian statistical gate timing analysisSoroush Abbaspour, Hanif Fatemi, Massoud Pedram. 947-952 [doi]
- Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltageSarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula. 953-958 [doi]
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