Noriaki Oda - researchr alias

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Viewing Publication 1 - 5 from 5

2008

2007

Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS GenerationNoriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno. ieicet, 90-C(4):848-855, 2007. [doi]

2006

Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and BeyondNoriaki Oda, Hiroyuki Kunishima, Takashi Kyouno, Kazuhiro Takeda, Tomoaki Tanaka, Toshiyuki Takewaki, Masahiro Ikeda. ieicet, 89-C(11):1544-1550, 2006. [doi]

Statistical corner conditions of interconnect delay (corner LPE specifications)Kenta Yamada, Noriaki Oda. aspdac 2006: 706-711 [doi]

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