Sudarshan Banerjee - researchr alias

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Viewing Publication 1 - 19 from 19

2010

Bandwidth Management in Application Mapping for Dynamically Reconfigurable ArchitecturesSudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt. trets, 3(3):18, 2010. [doi]

2009

Strip packing with precedence constraints and strip packing with release timesJohn Augustine, Sudarshan Banerjee, Sandy Irani. TCS, 410(38-40):3792-3803, 2009. [doi]

Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural ConsiderationsSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. tvlsi, 17(2):234-247, 2009. [doi]

2008

Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policiesMinyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian. tecs, 7(2), 2008. [doi]

2007

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable ArchitecturesSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera. dac 2007: 771-776 [doi]

Energy-aware co-processor selection for embedded processors on FPGAsAmir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee. iccd 2007: 158-163 [doi]

2006

Strip packing with precedence constraints and strip packing with release timesJohn Augustine, Sudarshan Banerjee, Sandy Irani. spaa 2006: 180-189 [doi]

PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architecturesSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt. aspdac 2006: 491-496 [doi]

Minimizing peak power for application chains on architectures with partial dynamic reconfigurationSudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt. fpt 2006: 273-276 [doi]

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic ReconfigurationSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. tvlsi, 14(11):1189-1202, 2006. [doi]

ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processorsPartha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne. tvlsi, 14(7):754-762, 2006. [doi]

Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft CorePartha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi. vlsid 2006: 651-656 [doi]

Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policiesMinyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian. codes 2006: 16-21 [doi]

2005

2004

FIFO power optimization for on-chip networksSudarshan Banerjee, Nikil D. Dutt. glvlsi 2004: 187-191 [doi]

Efficient search space exploration for HW-SW partitioningSudarshan Banerjee, Nikil D. Dutt. codes 2004: 122-127 [doi]

1997

Parallel Algorithms for Finding the Most Vital Edge in Weighted GraphsSudarshan Banerjee, Sanjeev Saxena. jpdc, 46(1):101-104, 1997.

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