Table of Contents

• Future challenges in embedded systemsAndrea Cuomo. 1 [doi]
• Organic computing: on the feasibility of controlled emergenceChristian Müller-Schloer. 2-5 [doi]
• A loop accelerator for low power embedded VLIW processorsBinu K. Mathew, Al Davis. 6-11 [doi]
• Dual-pipeline heterogeneous ASIP designSwarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran. 12-17 [doi]
• Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architecturesScott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer. 18-23 [doi]
• Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesisHyunuk Jung, Soonhoi Ha. 24-29 [doi]
• Efficient mapping of hierarchical trees on coarse-grain reconfigurable architecturesFredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh. 30-35 [doi]
• Detecting overflow detectionVladimir Kotlyar, Mayan Moudgill. 36-41 [doi]
• Memory accesses management during high level synthesisGwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin. 42-47 [doi]
• Parallel programming models for a multi-processor SoC platform applied to high-speed traffic managementPierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu. 48-53 [doi]
• Benchmark-based design strategies for single chip heterogeneous multiprocessorsJoAnn M. Paul, Donald E. Thomas, Alex Bobrek. 54-59 [doi]
• Automatic synthesis of system on chip multiprocessor architectures for process networksBasant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan. 60-65 [doi]
• Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulationXinping Zhu, Wei Qin, Sharad Malik. 66-71 [doi]
• Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches?Peter Marwedel, Catherine H. Gebotys. 72 [doi]
• Keynote: cellular handset technology system requirements and integration trendsSven Mattisson. 74 [doi]
• Transaction level modeling: flows and use modelsAdam Donlin. 75-80 [doi]
• Exploiting polymorphism in HW design: a case study in the ATM domainLuigi Pomante. 81-85 [doi]
• Facilitating reuse in hardware models with enhanced type inferenceManish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August. 86-91 [doi]
• System-on-chip validation using UML and CWLQiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata. 92-97 [doi]
• Compiler-directed code restructuring for reducing data TLB energyMahmut T. Kandemir, Ismail Kadayif, Guilin Chen. 98-103 [doi]
• Dynamic overlay of scratchpad memory for energy minimizationManish Verma, Lars Wehmeyer, Peter Marwedel. 104-109 [doi]
• CPU scheduling for statistically-assured real-time performance and improved energy efficiencyHaisang Wu, Binoy Ravindran, E. Douglas Jensen, Peng Li. 110-115 [doi]
• Power-performance trade-offs for reconfigurable computingJuanjo Noguera, Rosa M. Badia. 116-121 [doi]
• Efficient search space exploration for HW-SW partitioningSudarshan Banerjee, Nikil D. Dutt. 122-127 [doi]
• Tuning SoC platforms for multimedia processing: identifying limits and tradeoffsAlexander Maxiaguine, Yongxin Zhu, Samarjit Chakraborty, Weng-Fai Wong. 128-133 [doi]
• Energy-efficient flash-memory storage systems with an interrupt-emulation mechanismChin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang. 134-139 [doi]
• Memory system design space exploration for low-power, real-time speech recognitionRajeev Krishna, Scott A. Mahlke, Todd M. Austin. 140-145 [doi]
• Analytical models for leakage power estimation of memory array structuresMahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir. 146-151 [doi]
• A timing-accurate HW/SW co-simulation of an ISS with SystemCLuca Formaggio, Franco Fummi, Graziano Pravadelli. 152-157 [doi]
• RTOS-centric hardware/software cosimulator for embedded system designShinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada. 158-163 [doi]
• Fast co-simulation of transformative systems with OS support on SMP computerZhengting He, Aloysius K. Mok. 164-169 [doi]
• Power-aware communication optimization for networks-on-chips with voltage scalable linksDongkun Shin, Jihong Kim. 170-175 [doi]
• Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clockingErland Nilsson, Johnny Öberg. 176-181 [doi]
• Multi-objective mapping for mesh-based NoC architecturesGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi. 182-187 [doi]
• Optimizing the memory bandwidth with loop fusionPaul Marchal, José Ignacio Gómez, Francky Catthoor. 188-193 [doi]
• Operation tables for scheduling in the presence of incomplete bypassingAviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau. 194-199 [doi]
• A novel deadlock avoidance algorithm and its hardware implementationJaehwan Lee, Vincent John Mooney III. 200-205 [doi]
• Design and programming of embedded multiprocessors: an interface-centric approachPieter van der Wolf, Erwin A. de Kock, Tomas Henriksson, Wido Kruijtzer, Gerben Essink. 206-217 [doi]
• Current flattening in software and hardware for security applicationsRadu Muresan, Catherine H. Gebotys. 218-223 [doi]
• Low energy security optimization in embedded cryptographic systemsCatherine H. Gebotys. 224-229 [doi]
• Analyzing heap error behavior in embedded JVM environmentsGuilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin. 230-235 [doi]
• Power analysis of system-level on-chip communication architecturesKanishka Lahiri, Anand Raghunathan. 236-241 [doi]
• Fast exploration of bus-based on-chip communication architecturesSudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane. 242-247 [doi]
• Efficient exploration of on-chip bus architectures and memory allocationSungchan Kim, Chaeseok Im, Soonhoi Ha. 248-253 [doi]
• Embedded systems education: how to teach the required skills?Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist. 254-255 [doi]