Table of Contents

• UML and model-driven development for SoC designWolfgang Mueller, Yves Vanderperren. 1 [doi]
• Automotive electronics system, software, and local area networkYoshimi Furukawa, Seiji Kawamura. 2 [doi]
• Promises and challenges of mobile embedded system: : an industry perspectiveNam Sung Woo. 3 [doi]
• Application-specific workload shaping in multimedia-enabled personal mobile devicesBalaji Raman, Samarjit Chakraborty. 4-9 [doi]
• Efficient computation of buffer capacities for multi-rate real-time systems with back-pressureMaarten Wiggers, Marco Bekooij, Pierre G. Jansen, Gerard J. M. Smit. 10-15 [doi]
• Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policiesMinyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian. 16-21 [doi]
• Battery discharge aware energy feasibility analysisHenrik Lipskoch, Karsten Albers, Frank Slomka. 22-27 [doi]
• A run-time, feedback-based energy estimation model For embedded devicesSelim Gurun, Chandra Krintz. 28-33 [doi]
• Hardware based frequency/voltage control of voltage frequency island systemsPuru Choudhary, Diana Marculescu. 34-39 [doi]
• A formal approach to robustness maximization of complex heterogeneous embedded systemsArne Hamann, Razvan Racu, Rolf Ernst. 40-45 [doi]
• Automatic run-time extraction of communication graphs from multithreaded applicationsAi-Hsin Liu, Robert P. Dick. 46-51 [doi]
• The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applicationsDong-Ik Ko, Shuvra S. Bhattacharyya. 52-57 [doi]
• TLM/network design space exploration for networked embedded systemsNicola Bombieri, Franco Fummi, Davide Quaglia. 58-63 [doi]
• Automatic generation of transaction level models for rapid design space explorationDongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski. 64-69 [doi]
• Accurate yet fast modeling of real-time communicationGunar Schirner, Rainer Dömer. 70-75 [doi]
• Bounded arbitration algorithm for QoS-supported on-chip communicationMohammad Abdullah Al Faruque, Gereon Weiss, Jörg Henkel. 76-81 [doi]
• Increasing the throughput of an adaptive router in network-on-chip (NoC)Seung Eun Lee, Nader Bagherzadeh. 82-87 [doi]
• Automatic phase detection for stochastic on-chip traffic generationAntoine Scherrer, Antoine Fraboulet, Tanguy Risset. 88-93 [doi]
• Methodology for attack on a Java-based PDACatherine H. Gebotys, Brian A. White. 94-99 [doi]
• Hardware assisted pre-emptive control flow checking for embedded processors to improve reliabilityRoshan G. Ragel, Sri Parameswaran. 100-105 [doi]
• Architectural support for safe software execution on embedded processorsDivya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. 106-111 [doi]
• Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochipsTao Xu, Krishnendu Chakrabarty. 112-117 [doi]
• Floorplan driven leakage power aware IP-based SoC design space explorationAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. 118-123 [doi]
• Thermal-aware high-level synthesis based on network flow methodPilok Lim, Taewhan Kim. 124-129 [doi]
• A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow controlMartijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli. 130-135 [doi]
• Layout aware design of mesh based NoC architecturesKrishnan Srinivasan, Karam S. Chatha. 136-141 [doi]
• A methodology for design of application specific deadlock-free routing algorithms for NoC systemsMaurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania. 142-147 [doi]
• Retargetable code optimization with SIMD instructionsManuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren. 148-153 [doi]
• Pack instruction generation for media pUsing multi-valued decision diagramHiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa. 154-159 [doi]
• Automatic selection of application-specific instruction-set extensionsCarlo Galuzzi, Elena Moscu Panainte, Yana Yankova, Koen Bertels, Stamatis Vassiliadis. 160-165 [doi]
• Are current ESL tools meeting the requirements of advanced embedded systems?Jürgen Teich. 166 [doi]
• SHAPES: : a tiled scalable software hardware architecture platform for embedded systemsPier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini. 167-172 [doi]
• Challenges in exploitation of loop parallelism in embedded applicationsArun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito. 173-180 [doi]
• Resource virtualization in real-time CORBA middlewareChristopher D. Gill. 181-186 [doi]
• Phase guided sampling for efficient parallel application simulationJeffrey Namkung, Dohyung Kim, Rajesh K. Gupta, Igor Kozintsev, Jean-Yves Bouguet, Carole Dulong. 187-192 [doi]
• A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulationWei Qin, Joseph D Errico, Xinping Zhu. 193-198 [doi]
• B:::2:::Sim: : a fast micro-architecture simulator based on basic block characterizationWonbok Lee, Kimish Patel, Massoud Pedram. 199-204 [doi]
• Decision-theoretic exploration of multiProcessor platformsGiovanni Beltrame, Dario Bruschi, Donatella Sciuto, Cristina Silvano. 205-210 [doi]
• Multi-processor system design with ESPAMHristo Nikolov, Todor Stefanov, Ed F. Deprettere. 211-216 [doi]
• Heterogeneous multiprocessor implementations for JPEG: : a case studySeng Lin Shee, Andrea Erdos, Sri Parameswaran. 217-222 [doi]
• Fuzzy decision making in embedded system designAlessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania. 223-228 [doi]
• Demand paging for OneNAND:::TM::: Flash eXecute-in-placeYongsoo Joo, Yongseok Choi, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang. 229-234 [doi]
• Creation and utilization of a virtual platform for embedded software optimization: : an industrial case studySungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo. 235-240 [doi]
• Application specific forwarding network and instruction encoding for multi-pipe ASIPsSwarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic. 241-246 [doi]
• A bus architecture for crosstalk elimination in high performance processor designWen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang. 247-252 [doi]
• Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizationsAntonis Papanikolaou, T. Grabner, Miguel Miranda, P. Roussel, Francky Catthoor. 253-258 [doi]
• A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPHHayden Kwok-Hay So, Artem Tkachenko, Robert W. Brodersen. 259-264 [doi]
• Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systemsKrisztián Flautner. 265 [doi]
• Key technologies for the next generation wireless communicationsKyung Ho Kim. 266-269 [doi]
• Streamroller: : automatic synthesis of prescribed throughput accelerator pipelinesManjunath Kudlur, Kevin Fan, Scott A. Mahlke. 270-275 [doi]
• Increasing hardware efficiency with multifunction loop acceleratorsKevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke. 276-281 [doi]
• Generic netlist representation for system and PE level design explorationBita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski. 282-287 [doi]
• Integrated analysis of communicating tasks in MPSoCsSimon Schliecker, Matthias Ivers, Rolf Ernst. 288-293 [doi]
• Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applicationsIlya Issenin, Nikil Dutt. 294-299 [doi]
• System-level power-performance trade-offs in bus matrix communication architecture synthesisSudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt. 300-305 [doi]