- Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai. A 0.05-1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications. IEEE Trans. VLSI Syst., 33(1):35-46, January 2025.
- Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu. DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow. IEEE Trans. VLSI Syst., 33(7):1858-1871, July 2025.
- Hui Hu, Bingbing Yao, Yi Shan, Lei Qiu 0002. A Histogram-Based Calibration Algorithm of Capacitor Mismatch for SAR ADCs. IEEE Trans. VLSI Syst., 33(3):872-876, March 2025.
- Feng Bu, Ruixue Ding, Depeng Sun, Ge Wang, Yuan Gao, Rong Zhou, Xiaoteng Zhao, Lisheng Chen, Shubin Liu, Zhangming Zhu. A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration. IEEE Trans. VLSI Syst., 33(5):1442-1446, May 2025.
- Mahsa Zareie, Kamal El-Sankary, Dalton Martini Colombo, Ezz I. El-Masry. A Time-Domain Frequency Analyzer Based on Goertzel Algorithm. IEEE Trans. VLSI Syst., 33(6):1516-1529, June 2025.
- Le Chen, Yue Cao, Lin Ling, Shubin Liu, Haolin Han. Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC. IEEE Trans. VLSI Syst., 33(6):1794-1798, June 2025.
- Huaguo Liang, Jiahui Xiao, Xianrui Dou, Tianming Ni, Yingchun Lu, Zhengfeng Huang. A TSV Misalignment-Based Repair Architecture in 3-D Chips. IEEE Trans. VLSI Syst., 33(7):1816-1825, July 2025.
- Taeseung Kang, Jeonghyu Yang, Eunji Song, Seungwoo Son, Hyuntae Kim, Jaeduk Han. ppd PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology. IEEE Trans. VLSI Syst., 33(7):2084-2088, July 2025.
- Ehab A. Hamed, Gordy Carichner, Delbert A. Green II, Hun-Seok Kim, Inhee Lee 0001. Hybrid Timestamping Using Crystal and RC Oscillators for Shock-Resistant Precision. IEEE Trans. VLSI Syst., 33(7):2004-2008, July 2025.
- Jinming Zhang, Zhihong Chen, Yaoyao Ye, Hao Chen, Xiao Han, Jianfei Jiang 0001, Weiguang Sheng, Ningyi Xu, Yong Lian 0001, Guanghui He. IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems. IEEE Trans. VLSI Syst., 33(9):2424-2437, September 2025.