Table of Contents

• Program Committee [doi]
• Organizing Committee [doi]
• VLSI Design 2005 Conference Awards [doi]
• Reviewers [doi]
• Message from the Organizing Chair [doi]
• Embedded Systems Design Conference History [doi]
• Call for Participation: 10th IEEE VLSI Design & Test Symposium [doi]
• VLSI Design 2006 Conference Awards [doi]
• Call for Participation: VLSI Design 2007 [doi]
• VLSI Design Conference History [doi]
• Message from the General Chairs [doi]
• Message from the Program Chairs [doi]
• Conference Committee [doi]
• Low-Power Design Strategies for Mobile ComputingA. V. S. S. Prasad, Jacob Mathews, Nagi Naganathan. 3-4 [doi]
• Technology Impacts on Sub-90nm CMOS Circuit Design and Design MethodologiesRuchir Puri, Tanay Karnik, Rajiv V. Joshi. 5-7 [doi]
• Beyond RTL: Advanced Digital System DesignShiv Tasker, Rishiyur S. Nikhil. 8-9 [doi]
• System Aspects of Analog to Digital Converter DesignsShanthi Pavan, Prakash Easwaran, C. Srinivasan. 10 [doi]
• Interconnect Process Variations: Theory and PracticeN. S. Nagaraj. 11 [doi]
• Design Challenges for High Performance Nano-TechnologyGoutam Debnath, Paul J. Thadikaran. 12-13 [doi]
• DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product YieldDavid Abercrombie, Bernd Koenemann, Nagesh Tamarapalli, Srikanth Venkataraman. 14 [doi]
• A Comprehensive SoC Design Methodology for Nanometer Design ChallengesR. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude. 15-17 [doi]
• Sequential Equivalence CheckingAnmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra. 18-19 [doi]
• Embedded Systems Design Using FPGAParimal Patel. 20 [doi]
• Design of Embedded Systems with Novel ApplicationsRobert C. Lacovara, Dhadesugoor R. Vaman. 21-22 [doi]
• Small, Smart, Intelligent and Interactive Handheld DevicesDavid E. Orton. 25 [doi]
• We Want It All, and We Want It Now!Richard Miller. 29 [doi]
• Keynote AddressMatthew Rhodes. 30 [doi]
• IC/FPGA-Package-PCB Design CollaborationHenry Potts. 31 [doi]
• The Technological and Geographical Migration of the Semiconductor IndustryJackson Hu. 35 [doi]
• Future FPGA Technologies, in Partnership with UniversitiesRichard Sevcik. 36 [doi]
• UNUM: A Tinker-Toy Approach to Building Multicore PowerPC MicroarchitecturesArvind. 39 [doi]
• SoC - The Road AheadMahesh Mehendale. 40 [doi]
• Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic ResearchAndreas Kuehlmann. 41 [doi]
• Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS TechnologiesK. Narasimhulu, V. Ramgopal Rao. 45-50 [doi]
• Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode CircuitsM. S. Bhat, S. Rekha, H. S. Jamadagni. 51-56 [doi]
• Design of a 1 V Low Power 900 MHz QVCOPrabir K. Saha, Ashudeb Dutta, A. Patra, T. K. Bhattacharyya. 57-62 [doi]
• 16-Bit Segmented Type Current Steering DAC for Video ApplicationsGaurav Raja, Basabi Bhaumik. 63-68 [doi]
• A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOSSubhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya. 69-74 [doi]
• A Low Power 6-Bit A/D Converter Achieving 10-Bit Resolution for MEMS Sensor Interface Using Time-Interleaved Delta ModulationKoushik De, Santiram Kal. 75-80 [doi]
• Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS CircuitsSaraju P. Mohanty, Elias Kougianos. 83-88 [doi]
• Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display SystemsJayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown. 89-93 [doi]
• Wide Limited Switch Dynamic Logic Circuit ImplementationsThara Rejimon, Sanjukta Bhanja. 94-99 [doi]
• A Stimulus-Free Probabilistic Model for Single-Event-Upset SensitivityMohammad Gh. Mohammad, Laila Terkawi, Muna Albasman. 100-107 [doi]
• Phase Change Memory FaultsM. Jagadesh Kumar, Ali A. Orouji. 108-112 [doi]
• A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light LatencyPeter Caputa, Christer Svensson. 117-122 [doi]
• Optimization of Global Interconnects in High Performance VLSI CircuitsMin Tang, Jun-Fa Mao. 123-128 [doi]
• A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy FillsShabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure. 129-134 [doi]
• MoM - A Process Variation Aware Statistical Capacitance ExtractorRohit Ananthakrishna, Shabbir H. Batterywala. 135-140 [doi]
• Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment MetricsAmitava Bhaduri, Ranga Vemuri. 141-146 [doi]
• Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global RoutingJin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen. 147-152 [doi]
• A New Device Level Digital Simulator for Simulation and Functional Verification of Large Semiconductor MemoriesTathagato Rai Dastidar, Partha Ray. 155-160 [doi]
• An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-ChipHari Vijay Venkatanarayanan, Michael L. Bushnell. 161-168 [doi]
• Test Cost Reduction Using Partitioned Grid Random Access ScanDong Hyun Baik, Kewal K. Saluja. 169-174 [doi]
• An Efficient Scan Tree Design for Compact Test Pattern SetShibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya. 175-180 [doi]
• On Methods to Improve Location Based Logic DiagnosisWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang. 181-187 [doi]
• Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and CircuitsPalkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil. 188-193 [doi]
• A Wide-Range, High-Resolution, Compact CMOS, Time to Digital ConverterV. Ramakrishnan, Poras T. Balsara. 197-202 [doi]
• Programmable LDPC Decoder Based on the Bubble-Sort AlgorithmRohit Singhal, Gwan S. Choi, Rabi N. Mahapatra. 203-208 [doi]
• An Asynchronous Interconnect Architecture for Device Security EnhancementSimon Hollis, Simon W. Moore. 209-215 [doi]
• A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto ProcessorTong Zhou, Mingyan Yu, Yizheng Ye. 216-221 [doi]
• Checking Nested Properties Using Bounded Model Checking and Sequential ATPGQiang Qiang, Daniel G. Saab, Jacob A. Abraham. 225-230 [doi]
• Apriori Formal Coverage Analysis for Protocol PropertiesPraveen Tiwari, Saptarshi Biswas, Raj S. Mitra. 231-236 [doi]
• An Integrated Approach for Combining BDD and SAT ProversRolf Drechsler, Görschwin Fey, Sebastian Kinder. 237-242 [doi]
• Reducing Design Verification Cycle Time through Testbench RedundancyAman Kokrady, Theo J. Powell, S. Ramakrishnan. 243-248 [doi]
• CAD Tools for a Globally Asynchronous Locally Synchronous FPGA ArchitectureXin Jia, Ranga Vemuri. 251-256 [doi]
• Heterogeneous Floorplanning for FPGAsYan Feng, Dinesh P. Mehta. 257-262 [doi]
• A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive FiltersMark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson. 263-268 [doi]
• Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless CommunicationAmit Kumar 0002, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda. 271-276 [doi]
• A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay SignoffK. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu. 277-282 [doi]
• A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk NoiseNarender Hanchate, Nagarajan Ranganathan. 283-290 [doi]
• Instruction-Set-Extension Exploration Using Decomposable Heuristic SearchSamik Das, P. P. Chakrabarti, Pallab Dasgupta. 293-298 [doi]
• Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded ProcessorsNachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha. 299-304 [doi]
• Handling Constraints in Multi-Objective GA for Embedded System DesignBiman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury. 305-310 [doi]
• A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic ArrayAhsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu. 311-316 [doi]
• State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to NanotechnologiesRui Zhang, Niraj K. Jha. 317-322 [doi]
• Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing AnalysisJayashree Sridharan, Tom Chen. 323-328 [doi]
• An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power EfficiencyR. G. Raghavendra, Pradip Mandal. 331-336 [doi]
• Efficient Design and Analysis of Robust Power Distribution MeshesPuneet Gupta, Andrew B. Kahng. 337-342 [doi]
• Test Pattern Generation for Power Supply Droop FaultsDebasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu. 343-348 [doi]
• Bounding Supply Noise Induced Path Delay Variation Using a Relaxation ApproachBaohua Wang, Pinaki Mazumder. 349-354 [doi]
• Accurate Substrate Noise Analysis Based on Library Module CharacterizationSubodh M. Reddy, Rajeev Murgai. 355-362 [doi]
• Efficient Techniques for Noise Characterization of Sequential Cells and MacrosVenkat Rao Vallapenani, Ravi Shankar Chevuri, Bingxiong Xu, Lun Ye, Kanad Chakraborty. 363-368 [doi]
• An Approach to Architectural Enhancement for Embedded Speech ApplicationsSoumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay, Anupam Basu. 371-376 [doi]
• A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined AccumulatorJun Chen, Rong Luo, Huazhong Yang, Hui Wang. 377-380 [doi]
• Performance Optimization with Scalable Reconfigurable Computing SystemsRama Sangireddy, Prabhu Rajamani, Shwetha Gaddam. 381-386 [doi]
• Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r FormatHimanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas. 387-392 [doi]
• An Efficient and Accurate Logarithmic Multiplier Based on Operand DecompositionVenkataraman Mahalingam, N. Ranganathan. 393-398 [doi]
• Partial Product Reduction Based on Look-Up TablesHiginio Mora Mora, Jerónimo Mora Pascual, José-Luis Sánchez Romero, F. Pujol López. 399-404 [doi]
• Sequential Spectral ATPG Using the Wavelet Transform and CompactionSuresh Kumar Devanathan, Michael L. Bushnell. 407-412 [doi]
• Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay FaultsShweta Chary, Michael L. Bushnell. 413-418 [doi]
• New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant LogicGang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski. 419-424 [doi]
• On the Size and Generation of Minimal N-Detection TestsKalyana R. Kantipudi. 425-430 [doi]
• Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test FaultsLoganathan Lingappan, Niraj K. Jha. 431-436 [doi]
• Low-Cost Production Testing of Wireless TransmittersAchintya Halder, Abhijit Chatterjee. 437-442 [doi]
• Double-Gate SOI Devices for Low-Power and High-Performance ApplicationsKaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici. 445-452 [doi]
• Carbon Nanotube ElectronicsAli Javey, Hongjie Dai. 453-458 [doi]
• Design of Heterogeneous Embedded Systems Using DFCharts Model of ComputationIvan Radojevic, Zoran A. Salcic, Partha S. Roop. 461-464 [doi]
• Dynamic Template Generation for Resource Sharing in Control and Data Flow GraphsDavid Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee. 465-468 [doi]
• Recovery-Based Real-Time Static Scheduling for Battery Life OptimizationAnirban Lahiri, Saurabh Agarwal, Anupam Basu, Bhargab B. Bhattacharya. 469-472 [doi]
• Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible ProcessorsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 473-476 [doi]
• An Automatic Code Generation Tool for Partitioned Software in Distributed SystemsViswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh. 477-480 [doi]
• A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) AlgorithmNaga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty. 481-484 [doi]
• Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array OperationMotoi Ichihashi, Haruki Toda. 487-490 [doi]
• A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global InterconnectsAshok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar. 491-494 [doi]
• A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS TechnologySanjeev K. Jain, Pankaj Agarwal. 495-498 [doi]
• SEAT-LA: A Soft Error Analysis Tool for Combinational LogicR. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 499-502 [doi]
• Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG)Siva Embanath, Ramakrishnan Venkata. 503-506 [doi]
• An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAsVivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti. 507-510 [doi]
• Optimized VLIW Architecture for Non-zero IF QAM-Modem ImplementationsAlok Kumar Pani, Ratnam V. Raja Kumar. 513-516 [doi]
• Ultra Folded High-Speed Architectures for Reed-Solomon DecodersKavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti. 517-520 [doi]
• A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation MicrosystemsMian Dong, Chun Zhang, Songping Mai, Zhihua Wang, Dongmei Li. 521-524 [doi]
• Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit RemovalSimon Ogg, Bashir M. Al-Hashimi. 525-529 [doi]
• Novel Architecture of EBC for JPEG2000Anand Gautam, A. Geeta Madhuri, Priya Khandelwal, K. Pratyush Aditya, Meghana Desai, Padma N. Krishna, Malvika Dutt, Reeti Bhatia. 530-533 [doi]
• Real Time Dynamic Receive Apodization for an Ultrasound Imaging SystemJ. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee. 534-537 [doi]
• Design Planning for Uniform Thermal DistributionRajendra M. Patrikar, Olivier Peyran. 541-544 [doi]
• Solving Thermal Problems of Hot Chips Using Voronoi DiagramsSubhashis Majumder, Bhargab B. Bhattacharya. 545-548 [doi]
• Design of Multi-bit SET Adder and Its Fault SimulationDeepanjan Datta, Samiran Ganguly. 549-552 [doi]
• Efficient Analog Performance Macromodeling via Sequential Design Space DecompositionMengmeng Ding, Ranga Vemuri. 553-556 [doi]
• A Single Supply Level Shifter for Multi-Voltage SystemsQadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri. 557-560 [doi]
• A Rail-to-Rail I/O Operational Amplifier with 0.5 gm Fluctuation Using Double P-channel Differential Input PairsZhiyuan Li, Mingyan Yu, Jianguo Ma. 563-568 [doi]
• High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All ApproachSrikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar. 569-574 [doi]
• ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance PerspectiveIvan Siu-Chuang Lu, Neil Weste, Sri Parameswaran. 575-580 [doi]
• Techniques for On-Chip Process Voltage and Temperature Detection and CompensationQadeer Ahmad Khan, G. K. Siddhartha, Divya Tripathi, Sanjay Kumar Wadhwa, Kulbhushan Misri. 581-586 [doi]
• Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear LoopDebashis Dutta, Ritesh Ujjwal, Swapna Banerjee. 587-592 [doi]
• An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADCSanjoy Kumar Dey, Swapna Banerjee. 593-598 [doi]
• Using Level Restoring Method for Dual Supply VoltageK. Sadeghi, M. Emadi, F. Farbiz. 601-605 [doi]
• Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware DesignMaryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak. 606-612 [doi]
• On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi DecoderKoushik Maharatna, Alfonso Troya, Milos Krstic, Eckhard Grass. 613-618 [doi]
• A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC DesignSushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural. 619-624 [doi]
• Generating Scalable Polynomial Models: Key to Low Power High Performance DesignsG. Girishankar, Shitanshu Tiwari. 625-630 [doi]
• Zero Steady State Current Power on Reset Circuit with Brown-Out DetectorSanjay Kumar Wadhwa, G. K. Siddhartha, Anand Gaurav. 631-636 [doi]
• Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded SystemsHaris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar. 639-644 [doi]
• Reinforcement Temporal Difference Learning Scheme for Dynamic Energy Management in Embedded SystemsViswanathan Lakshmi Prabha, Elwin Chandra Monie. 645-650 [doi]
• Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft CorePartha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi. 651-656 [doi]
• A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip NetworksThomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal. 657-664 [doi]
• Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering ParametersDharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla. 667-671 [doi]
• Efficient and Accurate EMC Analysis of High-Frequency VLSI SubnetworksGurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin. 672-676 [doi]
• Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded SystemsArnab Sarkar, P. P. Chakrabarti, Rajeev Kumar. 677-682 [doi]
• Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level ControlSandip Aine, P. P. Chakrabarti, Rajeev Kumar. 683-688 [doi]
• Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole ExtractionRitochit Chakraborty, Mukesh Ranjan, Ranga Vemuri. 689-694 [doi]
• Fast DC Analysis and Its Application to Combinatorial Optimization ProblemsGaurav Trivedi, Madhav P. Desai, H. Narayanan. 695-700 [doi]
• Hybrid CMOS/Molecular Electronic CircuitsMircea R. Stan, Garrett S. Rose, Matthew M. Ziegler. 703-708 [doi]
• All-Printed RFID Tags: Materials, Devices, and Circuit ImplicationsVivek Subramanian, Paul C. Chang, Daniel Huang, Josephine B. Lee, Steven E. Molesa, David R. Redinger, Steven K. Volkman. 709-714 [doi]
• Threshold Trimming Based Design of a CMOS Programmable Operational AmplifierRoopak Suri, C. M. Markan. 717-720 [doi]
• Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas SensorT. K. Bhattacharyya, Shreyas Sen, Debashis Mandal, S. K. Lahiri. 721-724 [doi]
• Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor ElectronicsEvangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson. 725-728 [doi]
• Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and AlgorithmsSoumendu Bhattacharya, Vishwanath Natarajan, Abhijit Chatterjee, Sankar Nair. 729-733 [doi]
• Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless SystemZahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan. 734-737 [doi]
• CMOS Integrated Circuit for Sensing ApplicationsSupriya S. Shanbhag. 738-741 [doi]
• Semi-Custom Design of Adiabatic Adder CircuitsV. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel. 745-748 [doi]
• Clockless Pipelining for Coarse Grain DatapathsAbdelhalim Alsharqawi, Abdel Ejnioui. 749-753 [doi]
• Exploring Logic Block Granularity in Leakage Tolerant FPGARajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara. 754-757 [doi]
• High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET HeaderKoushik K. Das, Shih-Hsien Lo, Ching-Te Chuang. 758-761 [doi]
• An Alternative Real-Time Filter Scheme to Block BufferingYen-Jen Chang. 762-765 [doi]
• Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth VariationAswath Oruganti, Nagarajan Ranganathan. 766-769 [doi]
• Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) RoutingAjay Joshi, Vinita V. Deodhar, Jeffrey A. Davis. 773-776 [doi]
• A Progressive Two-Stage Global Routing for Macro-Cell Based DesignsAlkan Cengiz, Tom Chen. 777-780 [doi]
• Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock DomainsSuresh Balasubramanian, Narayanan Natarajan, Olivier Franza, Chris Gianos. 781-785 [doi]
• SmartExtract: Accurate Capacitance Extraction for SOC DesignsUsha Narasimha, Anthony M. Hill, N. S. Nagaraj. 786-789 [doi]
• Linear Required-Arrival-Time Trees and their ConstructionParthasarathi Dasgupta, Prashant Yadava. 790-793 [doi]
• A Methodology for Switching Activity Based IO Powerpad OptimisationSnehashis Roy, Sukumar Jairam, H. Udayakumar. 794-797 [doi]
• Aliasing Analysis of Spectral Statistical Response Compaction TechniquesOmar I. Khan, Michael L. Bushnell. 801-806 [doi]
• Testing High-Speed IO Links Using On-Die CircuitryPriya Iyer, Shailendra Jain, Bryan Casper, Jason Howard. 807-810 [doi]
• PIDISC: Pattern Independent Design Independent Seed Compression TechniqueKedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar. 811-817 [doi]
• Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay FaultsShweta Chary, Michael L. Bushnell. 818-823 [doi]
• An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable ModulesRamesh C. Tekumalla. 824-827 [doi]
• The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition FaultsIrith Pomeranz, Sudhakar M. Reddy. 828-831 [doi]