Thara Rejimon - researchr alias

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Viewing Publication 1 - 5 from 5

2009

Probabilistic Error Modeling for Nano-Domain Logic CircuitsThara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja. tvlsi, 17(1):55-65, 2009. [doi]

2006

Wide Limited Switch Dynamic Logic Circuit ImplementationsThara Rejimon, Sanjukta Bhanja. vlsid 2006: 94-99 [doi]

A Timing-Aware Probabilistic Model for Single-Event-Upset AnalysisThara Rejimon, Sanjukta Bhanja. tvlsi, 14(10):1130-1139, 2006. [doi]

Reliability-centric probabilistic analysis of VLSI circuitsThara Rejimon. PhD thesis, University of South Florida, Tampa, USA, 2006. [doi]

2005

An Accurate Probalistic Model for Error DetectionThara Rejimon, Sanjukta Bhanja. vlsid 2005: 717-722 [doi]

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