Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti. An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. In 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India. pages 507-510, IEEE Computer Society, 2006. [doi]
Abstract is missing.