Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti. An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. In 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India. pages 507-510, IEEE Computer Society, 2006. [doi]
@inproceedings{GargCSK06,
title = {An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs},
author = {Vivek Garg and Vikram Chandrasekhar and Milagros Sashikánth and V. Kamakoti},
year = {2006},
doi = {10.1109/VLSID.2006.38},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.38},
tags = {optimization, architecture},
researchr = {https://researchr.org/publication/GargCSK06},
cites = {0},
citedby = {0},
pages = {507-510},
booktitle = {19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2502-4},
}