Shabbir H. Batterywala - researchr alias

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Viewing Publication 1 - 17 from 17

2015

2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple GridsNitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. vlsid 2015: 186-191 [doi]

2014

Fixing Double Patterning violations with look-aheadSambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala. aspdac 2014: 149-154 [doi]

2013

Automatic design rule correction in presence of multiple grids and track patternsNitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. dac 2013: 26 [doi]

2009

Efficient Analog/RF Layout Closure with Compaction Based LegalizationSubramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. vlsid 2009: 137-142 [doi]

2008

Cell Swapping Based Migration Methodology for Analog and Custom LayoutsShabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy. isqed 2008: 450-455 [doi]

On Efficient and Robust Constraint Generation for Practical Layout LegalizationSambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy. isqed 2008: 379-384 [doi]

2007

A 3-dimensional FEM Based Resistance ExtractionSubramanian Rajagopalan, Shabbir H. Batterywala. vlsid 2007: 565-570 [doi]

Impact of Modern Process Technologies on the Electrical Parameters of InterconnectsDebjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou. vlsid 2007: 875-880 [doi]

2006

MoM - A Process Variation Aware Statistical Capacitance ExtractorRohit Ananthakrishna, Shabbir H. Batterywala. vlsid 2006: 135-140 [doi]

A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy FillsShabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure. vlsid 2006: 129-134 [doi]

2005

Variance Reduction in Monte Carlo Capacitance ExtractionShabbir H. Batterywala, Madhav P. Desai. vlsid 2005: 85-90 [doi]

2004

Computing Silent Gate Models for Noise Analysis from Slew and Delay TablesShabbir H. Batterywala, Narendra V. Shenoy. vlsid 2004: 989-994 [doi]

2003

A Method to Estimate Slew and Delay in Coupled Digital CircuitsShabbir H. Batterywala, Narendra V. Shenoy. vlsid 2003: 411-416 [doi]

2002

Track assignment: a desirable intermediate step between global routing and detailed routingShabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou. iccad 2002: 59-66 [doi]

2001

Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc MultiportsShabbir H. Batterywala, H. Narayanan. vlsid 2001: 500 [doi]

1999

Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect NetworksShabbir H. Batterywala, H. Narayanan. vlsid 1999: 169-174

1997

A New Partitioning Strategy Based on Supermodular FunctionsSachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan. vlsid 1997: 32-37 [doi]

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