Abstract is missing.
- Personal and Portable: The Evolving DefinitionGene A. Frantz. 3 [doi]
- Living at the EdgeTed Vucurevich. 4 [doi]
- India-Building the Tall, Thin VLSI EngineerRajeev Madhavan. 5 [doi]
- Advances in VLSI Design and Product Development ChallengesA. Vasudevan. 6 [doi]
- High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity GapSandeep K. Shukla, Jean-Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta. 9-14 [doi]
- Design of Deep Sub-Micron CMOS CircuitsRajiv V. Joshi, Kaushik Roy. 15-16 [doi]
- Testing Embedded Cores and SOCs-DFT, ATPG and BIST SolutionsRubin A. Parekhji. 17 [doi]
- Specification and Design of Multi-Million Gate SOCsRamesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran. 18-19 [doi]
- ESD Reliability Challenges for RF/Mixed Signal Design & ProcessingNatarajan Mahadeva Iyer, M. K. Radhakrishnan. 20-21 [doi]
- System Support for Embedded ApplicationsKrithi Ramamritham, Kavi Arya. 22 [doi]
- Narrow Band Noise Suppression Scheme for improving Signal to Noise RatioAnantha Nag, K. Radhakrishna Rao. 25-29 [doi]
- A Path Sensitization Technique for Testing of Switched Capacitor CircuitsSounil Biswas, Baquer Mazhari. 30-35 [doi]
- A Novel RF Front-End Chipset For ISM Band Wireless ApplicationsPrashant Admane, Manoj Patasani, Biju Viswanathan. 36-41 [doi]
- Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25µm CMOSSaikat Sarkar, Padmanava Sen, Arvind Raghava, Sudipto Chakarborty, Joy Laskar. 42 [doi]
- Comparison of Heuristic Algorithms for Variable Partitioning in Circuit ImplementationMuthukumar Venkatesan, Henry Selvaraj. 51-57 [doi]
- Timing Minimization by Statistical Timing hMetis-based PartitioningCristinel Ababei, Kia Bazargan. 58-63 [doi]
- An Efficient Practical Heuristic For Good Ratio-Cut PartitioningSachin B. Patkar, H. Narayanan. 64-69 [doi]
- An Efficient Multi-Level Partitioning Algorithm for VLSI CircuitsJong-Sheng Cherng, Sao-Jie Chen. 70 [doi]
- Low Power Technology Mapping for LUT based FPGA A Genetic Algorithm Approach Rohit Pandey, Santanu Chattopadhyay. 79-84 [doi]
- Routability Prediction for Field Programmable Gate Arrays with a Routing HierarchyZhibin Dai, Dilip K. Banerji. 85-90 [doi]
- A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA DesignsManish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri. 91 [doi]
- Detailed Analysis of FIBL in MOS Transistors with High-K Gate DielectricsNihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao. 99-104 [doi]
- Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC sR. Srinivasan, Navakanta Bhat. 105-109 [doi]
- Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode ApplicationsNajeebuddin Hakim, V. Ramgopal Rao, J. Vasi. 110-115 [doi]
- A New Approach to Analyze a Sub-micron CMOS InverterManisha Pattanaik, Swapna Banerjee. 116-121 [doi]
- Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology nodeVinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau. 122-127 [doi]
- Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuitsD. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao. 128 [doi]
- Effects of Multi-cycle Sensitization on Delay TestsArun Krishnamachary, Jacob A. Abraham. 137-142 [doi]
- Exclusive Test and its Applications to Fault DiagnosisVishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja. 143-148 [doi]
- A Fault-Independent Transitive Closure Algorithm for Redundancy IdentificationVishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell. 149-154 [doi]
- Exploiting Ghost-FSMs as a BIST Structure for Sequential MachinesSamir Roy, U. Maulik, Biplab K. Sikdar. 155-160 [doi]
- Design Of A Universal BIST (UBIST) StructureSukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri. 161-166 [doi]
- SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMsPetros Drineas, Yiorgos Makris. 167 [doi]
- Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocksRohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar. 177-182 [doi]
- Design of a high speed string matching co-processor for NLPVadali Srinivasa Murty, P. C. Reghu Raj, S. Raman. 183-188 [doi]
- A New Reactive Processor with Architectural Support for Control Dominated Embedded SystemsPartha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli. 189-194 [doi]
- Processing and Scheduling Components in an Innovative Network Processor ArchitectureKyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis. 195-201 [doi]
- A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSISrikar Movva, S. Srinivasan. 202-207 [doi]
- A Memory Efficient 3-D DWT ArchitectureBipul Das, Swapna Banerjee. 208 [doi]
- Electrical Model For Program Disturb Faults in Non-Volatile MemoriesMohammad Gh. Mohammad, Kewal K. Saluja. 217-222 [doi]
- Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMsS. Mahapatra, S. Shukuri, Jeff Bude. 223-226 [doi]
- Analyzing Soft Errors in Leakage Optimized SRAM DesignVijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin. 227-233 [doi]
- The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM PerformanceLi Ding 0002, Pinaki Mazumder. 234 [doi]
- Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG EnginesDaniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula. 243-248 [doi]
- Automating Formal Modular Verification of Asynchronous Real-Time Embedded SystemsPao-Ann Hsiung, Shu-Yu Cheng. 249-254 [doi]
- High Level Synthesis from Sim-nML Processor ModelsSouvik Basu, Rajat Moona. 255-260 [doi]
- Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency SynthesizersYong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang. 261 [doi]
- Embedding Security in Wireless Embedded SystemsSrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar. 269-270 [doi]
- Cryptosystem Designed for Embedded System SecuritySubhayan Sen, Sk. Iqbal Hossain, Kabirul Islam, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri. 271-276 [doi]
- A Pipeline Architecture for Encompression (Encryption + Compression) TechnologyChandrama Shaw, Debashis Chatterji, Pradipta Maji, Subhayan Sen, B. N. Roy, Parimal Pal Chaudhuri. 277-282 [doi]
- VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale ImagesAnnajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan. 283 [doi]
- Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS TechnologyKoushik K. Das, Richard B. Brown. 291-296 [doi]
- Resource Allocation and Binding Approach for Low Leakage PowerChandramouli Gopalakrishnan, Srinivas Katkoori. 297-302 [doi]
- Synthesis of Dual-VT Dynamic CMOS CircuitsDebasis Samanta, Ajit Pal. 303-308 [doi]
- A Low-Voltage Low Power CMOS Companding FilterJ. Veerendra Kumar, K. Radhakrishna Rao. 309-314 [doi]
- An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital DesignW. Kuang, J. S. Yuan. 315-319 [doi]
- A Methodology for Accurate Modeling of Energy Dissipation in Array StructuresMahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri. 320 [doi]
- Channel Width Test Data Compression under a Limited Number of Test Inputs and OutputsHideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa. 329-334 [doi]
- Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test SequencesIrith Pomeranz, Sudhakar M. Reddy. 335-340 [doi]
- Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-ChipsSantanu Chattopadhyay, K. Sudarsana Reddy. 341-346 [doi]
- Mutual Testing based on Wavelet TransformsC. P. Ravikumar, Nitin Kakkar, Saurabh Chopra. 347-352 [doi]
- New Graphical IDDQ Signatures Reduce Defect Level and Yield LossLan Rao, Michael L. Bushnell, Vishwani D. Agrawal. 353-360 [doi]
- Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier IdentificationSagar S. Sabade, D. M. H. Walker. 361 [doi]
- Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded SystemsJiong Luo, Niraj K. Jha. 369-375 [doi]
- Mapping and Scheduling for Architecture Exploration of Networking SoCsThomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer. 376-381 [doi]
- Interfacing Cores with On-chip Packet-Switched NetworksPraveen Bhojwani, Rabi N. Mahapatra. 382-387 [doi]
- Interface Design Techniques for Single-Chip SystemsRobert H. Bell Jr., Lizy Kurian John. 388-394 [doi]
- CMOS Digital Imager Design from a System-on-a-chip PerspectiveBedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang, Suresh Seshadri, Julie Heynssens, Chris Wrigley. 395-400 [doi]
- Extending Platform-Based Design to Network on Chip SystemsJuha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar. 401 [doi]
- A Method to Estimate Slew and Delay in Coupled Digital CircuitsShabbir H. Batterywala, Narendra V. Shenoy. 411-416 [doi]
- Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer StrategyVani Prasad, Madhav P. Desai. 417-422 [doi]
- Bridging Fault Detections for Testable Realizations of Logic FunctionsPan Zhongliang. 423 [doi]
- Efficient RTL Power Estimation for Large DesignsSrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar. 431-439 [doi]
- Transition Activity Estimation for General Correlated Data DistributionsAlberto García Ortiz, Tudor Murgan, Manfred Glesner. 440-445 [doi]
- Energy Efficient Scheduling for Datapath SynthesisSaraju P. Mohanty, N. Ranganathan. 446-451 [doi]
- A Game-Theoretic Approach for Binding in Behavioral SynthesisAshok K. Murugavel, N. Ranganathan. 452 [doi]
- SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler TransformationsSumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. 461-466 [doi]
- High-level Synthesis of Multi-process Behavioral DescriptionsWeidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey. 467-473 [doi]
- Graph Transformations for Improved Tree Height ReductionG. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja. 474-479 [doi]
- Task Graph Extraction for Embedded System SynthesisKeith S. Vallerio, Niraj K. Jha. 480 [doi]
- A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic DesignM. Jagadesh Kumar, D. Venkateshrao. 489-492 [doi]
- Comparison of Bistable Circuits Based on Resonant-Tunneling DiodesAlejandro F. González, Pinaki Mazumder. 493-492 [doi]
- A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS RegimeAbhisek Dixit, V. Ramgopal Rao. 499-503 [doi]
- A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and TemperatureQadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri. 504-506 [doi]
- Synthesis Of Programmable Current Mode Linear Analog CircuitBaidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh. 507-512 [doi]
- On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative AssessmentGeun Rae Cho, Tom Chen. 513 [doi]
- A Low Power-Delay Product Page-Based Address Bus Coding MethodChi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin. 521-526 [doi]
- Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear ProgramTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell. 527-532 [doi]
- GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State AssignmentGanesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz. 533-538 [doi]
- A Framework for Energy and Transient Power Reduction during Behavioral SynthesisSaraju P. Mohanty, N. Ranganathan. 539-545 [doi]
- Low-Energy BIST Design for Scan-based Logic CircuitsBhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang. 546-551 [doi]
- Genetic Algorithm based Approach for Low Power Combinational Circuit TestingSantanu Chattopadhyay, Naveen Choudhary. 552 [doi]
- A Run-Time Reconfigurable System for Gene-Sequence SearchingKiran Puttegowda, William Worek, Nicholas Pappas, Anusha Dandapani, Peter Athanas, Allan Dickerman. 561-566 [doi]
- A Run-time Reconfiguration Algorithm for VLSI ArraysWu Jigang, Thambipillai Srikanthan. 567-572 [doi]
- Optimal Code and Data Layout in Embedded SystemsT. S. Rajesh Kumar, R. Govindarajan, C. P. Ravi Kumar. 573-578 [doi]
- Synthesis of Real-Time Embedded Software by Timed Quasi-Static SchedulingPao-Ann Hsiung, Feng-Shi Su. 579-584 [doi]
- SoC Synthesis with Automatic Hardware Software Interface GenerationAmarjeet Singh 0002, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar. 585 [doi]