Geun Rae Cho - researchr alias

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Viewing Publication 1 - 10 from 10

2014

Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusabilityMoon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim. vlsi 2014: 1-6 [doi]

2013

A high supply voltage bandgap reference circuit using drain-extended MOS devicesGeun Rae Cho, Kyung Woon Hwang, Tag Gon Kim. ieiceee, 10(8):20130142, 2013. [doi]

2004

Synthesis of single/dual-rail mixed PTL/static logic for low-power applicationsGeun Rae Cho, Tom Chen. tcad, 23(2):229-242, 2004. [doi]

2003

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor LogicGeun Rae Cho, Tom Chen. isqed 2003: 55-60 [doi]

On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative AssessmentGeun Rae Cho, Tom Chen. vlsid 2003: 513 [doi]

2002

On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL SynthesisGeun Rae Cho, Tom Chen. iwls 2002: 289-294

On The Impact of Technology Scaling On Mixed PTL/Static CircuitsGeun Rae Cho, Tom Chen. iccd 2002: 322-326 [doi]

Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power ApplicationsGeun Rae Cho, Tom Chen. isqed 2002: 458-463 [doi]

Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power ApplicationsGeun Rae Cho, Tom Chen. seal 2004: 446-465 [doi]

2001

On Mixed PTL/Static Logic for Low-power and High-speed CircuitsGeun Rae Cho, Tom Chen. vlsi, 2001(3):399-406, 2001. [doi]

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