Abstract is missing.
- From IP to PlatformsRaul Camposano. [doi]
- Application Specific Embedded Processors for Next Generation Communication SystemsUlrich Ramacher. [doi]
- Supercomputing on a Chip: Evolution and ChallengesJustin R. Rattner. [doi]
- Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW ArchitectureAtsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui. 2-7 [doi]
- Low Power Design Methodologies for Mobile CommunicationRalf Kakerow. 8-13 [doi]
- Power-Constrained Microprocessor DesignH. Peter Hofstee. 14-16 [doi]
- Functional Verification of the IBM zSeries eServer z900 SystemJoerg Walter. 17 [doi]
- A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical InterconnectChung-Seok (Andy) Seo, Abhijit Chatterjee. 24-29 [doi]
- Physical Planning Of On-Chip Interconnect ArchitecturesHongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng. 30-35 [doi]
- An Efficient External-Memory Implementation of Region Query with Application to Area RoutingStan Y. Liao, Narendra V. Shenoy, William Nicholls. 36-41 [doi]
- GPE: A New Representation for VLSI Floorplan ProblemChang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang. 42-44 [doi]
- A Standard-Cell Placement Tool for Designs with High Row UtilizationXiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh. 45 [doi]
- k-time Forced Simulation: A Formal Verification Technique for IP ReusePartha S. Roop, Arcot Sowmya, S. Ramesh. 50-55 [doi]
- Checking Equivalence for Circuits Containing Incompletely Specified BoxesChristoph Scholl, Bernd Becker. 56-63 [doi]
- Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input OrderingFadi A. Aloul, Igor L. Markov, Karem A. Sakallah. 64-69 [doi]
- Environment Synthesis for Compositional Model CheckingHong Peng, Yassine Mokhtari, Sofiène Tahar. 70 [doi]
- Physical Design Challenges for Billion Transistor ChipsPatrick Groeneveld. 78-83 [doi]
- From ASIC to ASIP: The Next Design DiscontinuityKurt Keutzer, Sharad Malik, A. Richard Newton. 84-90 [doi]
- High Level Functional Verification ClosureSurrendra Dudani, Jayant Nagda. 91 [doi]
- A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box ArchitectureSumio Morioka, Akashi Satoh. 98-103 [doi]
- Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image ProcessingAlexander Taubin, Karl Fant, John McCardle. 104-111 [doi]
- A New Architecture for Signed Radix-2m Pure Array MultipliersEduardo A. C. da Costa, Sergio Bampi, José Monteiro. 112-117 [doi]
- A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance MicroprocessorsOguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev. 118-121 [doi]
- Analysis of Blocking Dynamic CircuitsTyler Thorp, Dean Liu. 122 [doi]
- Parallel Multiple-Symbol Variable-Length DecodingJari Nikara, Stamatis Vassiliadis, Jarmo Takala, Mihai Sima, Petri Liuha. 126-131 [doi]
- Analysis of the Tradeoffs for the Implementation of a High-Radix LogarithmJosé-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera. 132-137 [doi]
- Adaptive Balanced Computing (ABC) Microprocessor Using Reconfigurable Functional Caches (RFCs)Huesung Kim, Arun K. Somani, Akhilesh Tyagi. 138-144 [doi]
- Floating-Point Fused Multiply-Add with Reduced LatencyTomás Lang, Javier D. Bruguera. 145 [doi]
- Methodologies and Tools for Pipelined On-Chip InterconnectLouis Scheffer. 152-157 [doi]
- Timing Window Applications in UltraSPARC-IIIi? Microprocessor DesignRita Yu Chen, Paul Yip, Georgios Konstadinidis, Andrew Demas, Fabian Klass, Rob Mains, Margaret Schmitt, Dina Bistry. 158-163 [doi]
- A System-Level Solution to Domino Synthesis with 2 GHz ApplicationB. Chappell, X. Wang, P. Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain. 164 [doi]
- Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative StudyHongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Kevin B. Theobald. 174-179 [doi]
- Balancing the Interconnect Topology for Arrays of Processors between Cost and PowerEsther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham. 180-186 [doi]
- A Low Energy Set-Associative I-Cache with Extended BTBKoji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami. 187 [doi]
- Don t-Care Identification on Specific Bits of Test PatternsKohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy. 194-199 [doi]
- An Extended Class of Sequential Circuits with Combinational Test Generation ComplexityMichiko Inoue, Chikateru Jinno, Hideo Fujiwara. 200-205 [doi]
- On the Coverage of Delay Faults in Scan Designs with Multiple Scan ChainsIrith Pomeranz, Sudhakar M. Reddy. 206-209 [doi]
- A Test Processor Concept for Systems-on-a-ChipChristian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus. 210 [doi]
- Locating Tiny Sensors in Time and Space: A Case StudyLewis Girod, Vladimir Bychkovskiy, Jeremy Elson, Deborah Estrin. 214-219 [doi]
- A Distributed Computation Platform for Wireless Embedded SensingAndreas Savvides, Mani B. Srivastava. 220-225 [doi]
- System-Architectures for Sensor Networks Issues, Alternatives, and DirectionsJessica Feng, Farinaz Koushanfar, Miodrag Potkonjak. 226 [doi]
- Subword Sorting with Versatile Permutation InstructionsZhijie Shi, Ruby B. Lee. 234-241 [doi]
- Branch Behavior of a Commercial OLTP Workload on Intel IA32 ProcessorsMurali Annavaram, Trung A. Diep, John Paul Shen. 242-248 [doi]
- Performance Enhancements to the Active Memory SystemWitawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang. 249 [doi]
- Cost-Effective Concurrent Test Hardware Design for Linear Analog CircuitsSule Ozev, Alex Orailoglu. 258-264 [doi]
- Accurate and Efficient Static Timing Analysis with CrosstalkI-De Huang, Sandeep K. Gupta, Melvin A. Breuer. 265-272 [doi]
- On the Detectability of Parametric Faults in Analog CircuitsJacob Savir, Zhen Guo. 273-276 [doi]
- Using Offline and Online BIST to Improve System Dependability - The TTPC-C ExampleAndreas Steininger, Johann Vilanek. 277 [doi]
- The Imagine Stream ProcessorUjval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany. 282-288 [doi]
- VLSI Design and Verification of the Imagine ProcessorBrucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles. 289-294 [doi]
- Media Processing Applications on the Imagine Stream ProcessorJohn D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally. 295-302 [doi]
- A Stream Processor Development PlatformBen Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally. 303 [doi]
- Low-Power, High-Speed CMOS VLSI DesignTadahiro Kuroda. 310-315 [doi]
- Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power ReductionStephanie Augsburger, Borivoje Nikolic. 316-321 [doi]
- On The Impact of Technology Scaling On Mixed PTL/Static CircuitsGeun Rae Cho, Tom Chen. 322-326 [doi]
- Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined CircuitsShanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai. 327 [doi]
- Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area CostYen-Jen Chang, Feipei Lai, Shanq-Jang Ruan. 334-339 [doi]
- A Framework for Data Prefetching Using Off-Line Training of Markovian PredictorsJinwoo Kim, Krishna V. Palem, Weng-Fai Wong. 340-347 [doi]
- Trace Cache Performance ParametersAfzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen. 348-355 [doi]
- Data Cache Design Considerations for the Itanium:::®::: 2 ProcessorTerry Lyon, Eric DeLano, Cameron McNairy, Dean Mulla. 356 [doi]
- Requirements for Automotive System Engineering ToolsJoachim Schlosser. 364-369 [doi]
- Automotive Virtual Integration Platforms: Why s, What s, and How sPaolo Giusto, Jean-Yves Brunel, Alberto Ferrari, Eliane Fourgeau, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 370-378 [doi]
- Models of IP s for Automotive Virtual Integration PlatformsPaolo Giusto, Jean-Yves Brunel, Alberto Ferrari, Eliane Fourgeau, Luciano Lavagno, Barry O Rourke, Alberto L. Sangiovanni-Vincentelli, Emanuele Guasto. 379 [doi]
- Impact of Scaling on the Effectiveness of Dynamic Power Reduction SchemesDavid Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland. 382-387 [doi]
- Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input StreamsSanjukta Bhanja, N. Ranganathan. 388-390 [doi]
- Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive BehaviorsLin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha. 391-394 [doi]
- Accelerated SAT-based Scheduling of Control/Data Flow GraphsSeda Ogrenci Memik, Farzan Fallah. 395 [doi]
- Trace-Level Speculative Multithreaded ArchitectureCarlos Molina, Antonio González, Jordi Tubella. 402-407 [doi]
- Speculative Trace Scheduling in VLIW ProcessorsManvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan. 408-413 [doi]
- Embedded Protocol Processor for Fast and Efficient Packet ReceptionTomas Henriksson, Ulf Nordqvist, Dake Liu. 414 [doi]
- Fitted Elmore Delay: A Simple and Accurate Interconnect Delay ModelArif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu. 422-427 [doi]
- Exact Closed Form Formula for Partial Mutual Inductances of On-Chip InterconnectsGuoan Zhong, Cheng-Kok Koh. 428-433 [doi]
- Efficient PEEC-Based Inductance Extraction Using Circuit-Aware TechniquesHaitian Hu, Sachin S. Sapatnekar. 434 [doi]
- Applying Decay Strategies to Branch Predictors for Leakage Energy SavingsZhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi. 442-445 [doi]
- Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid ApproachAnn Gordon-Ross, Frank Vahid. 446-449 [doi]
- TTA-C2, A Single Chip Communication Controller for the Time-Triggered-ProtocolManfred Ley, Herbert Grünbacher. 450-453 [doi]
- Adaptive Pipeline Depth Control for Processor Power-ManagementAristides Efthymiou, Jim D. Garside. 454-457 [doi]
- Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance ProcessorsAmirali Baniasadi, Andreas Moshovos. 458-461 [doi]
- Improving Processor Performance by Simplifying and Bypassing Trivial ComputationsJoshua J. Yi, David J. Lilja. 462 [doi]
- A Low Power Pseudo-Random BIST TechniqueNadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz. 468-473 [doi]
- Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-SeedingPaul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici. 474-479 [doi]
- Fault Dictionary Size Reduction through Test Response SuperpositionBaris Arslan, Alex Orailoglu. 480 [doi]
- Designing an Asynchronous Microcontroller Using PipefitterIvan Blunno, Luciano Lavagno. 488-493 [doi]
- Legacy SystemC Co-Simulation of Multi-Processor Systems-on-ChipLuca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino. 494-499 [doi]
- A Design Methodology for Application-Specific Real-Time InterfacesStefan Ihmor, Markus Visarius, Wolfram Hardt. 500 [doi]
- TAXI: Trace Analysis for X86 InterpretationStevan A. Vlaovic, Edward S. Davidson. 508-514 [doi]
- Embedded Operating System Energy Analysis and Macro-ModelingTat Kee Tan, Anand Raghunathan, Niraj K. Jha. 515-520 [doi]
- SIMD Extension to VLIW Multicluster Processors for Embedded ApplicationsDomenico Barretta, William Fornaciari, Mariagiovanna Sami, Danilo Pau. 523-526 [doi]
- JMA: The Java-Multithreading Architecture for Embedded ProcessorsPanit Watcharawitch, Simon W. Moore. 527 [doi]