Tomás Lang, Javier D. Bruguera. Floating-Point Fused Multiply-Add with Reduced Latency. In 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings. pages 145, IEEE Computer Society, 2002. [doi]
Abstract is missing.