Abstract is missing.
- Integrating Yield, Test and Reliability: Statistical Models with Applications to Test and Burn-in Optimization Adit D. Singh. 7 [doi]
- Optimizing the Yield of VLSI CircuitsIsrael Koren, Julie D. Segal. 7 [doi]
- Test Structures for Circuit Yield Assessment and ModelingDuane S. Boning. 8 [doi]
- Testing and Yield of Integrated CircuitsZoran Stamenkovic. 8 [doi]
- Yield in flash memory: Methodology, modeling and design issuesGiuseppe Crisenza. 9 [doi]
- Design Based Yield Improvements (DBYI)Enrico Malavasi. 9 [doi]
- Enhancing the Silicon-Package Interface Through Their Concurrent Design and VerificationMarco Casale-Rossi. 10 [doi]
- An EDA Perspective, We Need it Yesterday!Anna Fontanelli. 11 [doi]
- An EDA Perspective, Let s do it Concurrently!Kevin Rinebold. 11 [doi]
- A Package Design Perspective, It will be BGA and Flip-Chip Rich Evans. 11 [doi]
- Noise Analysis for 0.13um and BeyondKen Tseng. 12 [doi]
- Overview of Reliability Issues in Deep Sub-Micron Digital CMOS Technology and Their Interaction with Circuit Design ConsiderationsMohsen Alavi. 12 [doi]
- NBTI/HCI Modeling and Full-Chip Analysis in Design EnvironmentLifeng Wu. 13-14 [doi]
- Is Quality a Design Constraint for Sub 100nm Designs?Steven Ohr. 15 [doi]
- Platform Leadership in the Ambient Intelligence Era21-22 [doi]
- Quality SoC Design and Implementation for Real Manufacturability23-24 [doi]
- Quality Challenges of the Nanometer Design Realm25 [doi]
- Leakage Current Reduction in Sequential Circuits by Modifying the Scan ChainsAfshin Abdollahi, Farzan Fallah, Massoud Pedram. 49-54 [doi]
- Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor LogicGeun Rae Cho, Tom Chen. 55-60 [doi]
- Design Techniques for Gate-Leakage Reduction in CMOS CircuitsRafik S. Guindi, Farid N. Najm. 61 [doi]
- Using Integer Equations for High Level Formal Verification Property CheckingBijan Alizadeh, Mohammad Reza Kakoee. 69-74 [doi]
- True Coverage: A Goal of VerificationGary Feierbach, Vijay Gupta. 75-78 [doi]
- Low-Cost and Real-Time Super-Resolution over a Video Encoder IPGustavo Marrero Callicó, Antonio Núñez, Rafael Peset Llopis, Ramanathan Sethuraman. 79-84 [doi]
- LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume ReductionJean-Pierre Heliot, Florent Parmentier, Marie-Pierre Baron. 85 [doi]
- Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable WrappersSandeep Koranne. 93-98 [doi]
- Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test SetsYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy. 99-104 [doi]
- Compact Dictionaries for Fault Diagnosis in BISTChunsheng Liu, Krishnendu Chakrabarty. 105-110 [doi]
- Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test PatternsChien-In Henry Chen, Kiran George. 111 [doi]
- Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and ManufacturabilityF. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh. 119-124 [doi]
- Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout SynthesisQi-De Qian, Sheldon X.-D. Tan. 125-130 [doi]
- New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design DomainsPradiptya Ghosh, Chung-shin Kang, Michael Sanie, David Pinto. 131-137 [doi]
- System and Framework for QA of Process Design KitsM. C. Scott, M. O. Peralta, Jo Dale Carothers. 138-143 [doi]
- The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data ExchangeGilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Sridhar Subramaniam, Hem Hingarh. 144 [doi]
- Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS CircuitsChing-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim. 153-158 [doi]
- Revisiting the Noise Figure Design Metric for Digital Communication ReceiverWon Namgoong, Jongrit Lerdworatawee. 159-162 [doi]
- Benchmarks for Interconnect Parasitic Resistance and CapacitanceN. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell. 163 [doi]
- Post-Route Gate Sizing for Crosstalk Noise ReductionMurat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj. 171-176 [doi]
- Noise-Aware Driver Modeling for Nanometer TechnologyXiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas. 177-182 [doi]
- Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change CharacteristicsTom Chen, Amjad Hajjar. 183-188 [doi]
- Modeling Crosstalk Induced DelayChung-Kuan Tsai, Malgorzata Marek-Sadowska. 189-194 [doi]
- A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC DesignHai Lan, Zhiping Yu, Robert W. Dutton. 195 [doi]
- Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing DeveloperTerry Blanchard. 203-207 [doi]
- Impact of Interoperability on CAD-IP Reuse: An Academic ViewpointAndrew B. Kahng, Igor L. Markov. 208-213 [doi]
- Interoperability Beyond Design: Sharing Knowledge between Design and ManufacturingD. R. Cottrell, T. J. Grebinski. 214 [doi]
- Advanced Module Packaging MethodPeter C. Salmon. 223-228 [doi]
- Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation PlatformMichael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming Dai. 229-234 [doi]
- Modeling and Analysis of Power Distribution Networks for Gigabit ApplicationsWendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim, Madhavan Swaminathan. 235-240 [doi]
- Active Device under Bond Pad to Save I/O Layout for High-pin-count SOCMing-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang. 241 [doi]
- Addressing the IC Designer s Needs: Integrated Design Software for Faster, More Economical Chip Design253-254 [doi]
- Closing the Gap between ASIC and Full Custom: A Path to Quality Design255-256 [doi]
- A VLSI System Perspective for Microprocessors Beyond 90nm257 [doi]
- Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line DriversSoroush Abbaspour, Massoud Pedram, Payam Heydari. 261-266 [doi]
- Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAsHyung Gyu Lee, Sungyuep Nam, Naehyuck Chang. 267-272 [doi]
- Quantifying Error in Dynamic Power Estimation of CMOS CircuitsPuneet Gupta, Andrew B. Kahng. 273-278 [doi]
- Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage OptimizationVolkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman. 279 [doi]
- Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS DesignDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester. 287-292 [doi]
- Design and Analysis of Low-Voltage Current-Mode Logic BuffersPayam Heydari. 293-298 [doi]
- Reduced-Order Modeling Based on PRONY s and SHANK s Methods via the Bilinear TransformationMakram M. Mansour, Amit Mehrotra. 299 [doi]
- A Novel Clocking Strategy for Dynamic CircuitsYoung-Jun Lee, Jong-Jin Lim, Yong-Bin Kim. 307-312 [doi]
- Procedural Analog Design (PAD) ToolDanica Stefanovic, Maher Kayal, Marc Pastre, Vanco B. Litovski. 313-318 [doi]
- Parameterized Macrocells with Accurate Delay Models for Core-Based DesignsMakram M. Mansour, Mohammad M. Mansour, Amit Mehrotra. 319 [doi]
- Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene TherapyWai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao. 327-332 [doi]
- Minimizing Inter-Clock Coupling JitterMing-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen. 333-338 [doi]
- A Proposal for Routing-Based Timing-Driven Scan Chain OrderingPuneet Gupta, Andrew B. Kahng, Stefanus Mantik. 339-343 [doi]
- Elimination of false aggressors using the functional relationship for full-chip crosstalk analysisJae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong. 344-347 [doi]
- PDL: A New Physical Synthesis MethodologyToshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura. 348 [doi]
- Statistical Modeling for Circuit SimulationColin C. McAndrew. 357-362 [doi]
- Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface CircuitsMing-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng. 363-368 [doi]
- Coupled Simulation of Circuit and Piezoelectric LaminatesChenggang Xu, Terri S. Fiez, Kartikeya Mayaram. 369-372 [doi]
- Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modelingWon-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, Jeong-Taek Kong. 373-376 [doi]
- Static Electromigration Analysis for Signal InterconnectsChanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta. 377 [doi]
- Hidden Quality, Crouching Customer - How Much Does the Quality of EDA Tools Impact Electronic Design?Tets Maniwa. 383 [doi]
- On-Chip Interconnect Inductance - Friend or Foe (Invited)S. Simon Wong, C. Patrick Yue, Richard Chang, So-Young Kim, Bendik Kleveland, Frank O Mahony. 389-394 [doi]
- Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect DelayTakashi Sato, Hiroo Masuda. 395-400 [doi]
- On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and BeyondSoyoung Kim, Yehia Massoud, S. Simon Wong. 401-404 [doi]
- Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design FlowPayman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright. 405-409 [doi]
- Analyzing Internal-Switching Induced Simultaneous Switching NoiseLi Yang, J. S. Yuan. 410 [doi]
- Generation of Hazard Identification FunctionsMaria K. Michael, Spyros Tragoudas. 419-424 [doi]
- Concurrent Fault Detection in Random Combinational LogicPetros Drineas, Yiorgos Makris. 425-430 [doi]
- Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT SchemesDaniela De Venuto, Michael J. Ohletz, Bruno Riccò. 431-437 [doi]
- On Structural vs. Functional Testing for Delay FaultsAngela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang. 438-441 [doi]
- An Embedded IDDQ Testing Architecture and TechniqueY. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni. 442 [doi]