Jeng-Jie Peng - researchr alias

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Viewing Publication 1 - 6 from 6

2003

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOCMing-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang. isqed 2003: 241 [doi]

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface CircuitsMing-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng. isqed 2003: 363-368 [doi]

2002

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuitsJeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang. iscas 2002: 537-540 [doi]

2001

ESD test methods on integrated circuits: an overviewMing-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang. icecsys 2001: 1011-1014 [doi]

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC'sMing-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh. icecsys 2001: 113-116 [doi]

1998

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technologyMing-Dou Ker, Jeng-Jie Peng. cicc 1998: 537-540 [doi]

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