Table of Contents

• MDSP-II: 16-bit DSP with mobile communication acceleratorByoung-Woon Kim, Jin-Hyuk Yang, Chan-Soo Hwang, Young-Su Kwon, Keun-Moo Lee, In-Hyoung Kim, Yong-Hoon Lee, Chong-Min Kyung. 5-8 [doi]
• A single chip DMT modem for high-speed WLANST. Arivoli 0001, Mark Bickerstaff, Philip J. Ryan, Tom McDermott, Neil Weste, David J. Skellern, Terence M. Percival. 9-11 [doi]
• A new scalable VLSI architecture for Reed-Solomon decodersWolfgang Wilhelm, A. Kaufmann, Tobias G. Noll. 13-16 [doi]
• An embedded stack microprocessor for SDH telecommunication applicationsManfred Stadler, Markus Thalmann, Thomas Röwer, Norbert Felber, Wolfgang Fichtner. 17-20 [doi]
• CMOS technology characterization for analog and RF designBehzad Razavi. 23-30 [doi]
• Nano-amp, active-bulk, weak-inversion analog circuitsRafael Fried, Christian C. Enz. 31-34 [doi]
• Current sensor IC provides 9 bit+sign result without external sense resisterJeff Kotowski, Bill McIntyre, John Parry. 35-38 [doi]
• On the exact design of RF oscillatorsQiuting Huang. 41-44 [doi]
• Phase noise and timing jitter in oscillatorsAlper Demir 0001, Amit Mehrotra, Jaijeet Roychowdhury. 45-48 [doi]
• Phase noise in multi-gigahertz CMOS ring oscillatorsAli Hajimiri, Sotirios Limotyrakis, Thomas H. Lee. 49-52 [doi]
• Nonlinear behavioral modeling and phase noise evaluation in phase locked loopsBart De Smedt, Georges G. E. Gielen. 53-56 [doi]
• Microwave CMOS-devices and circuitsTajinder Manku. 59-66 [doi]
• Broadband, 0.25 /spl mu/m CMOS LNAs with sub-2dB NF for GSM applicationsQiuting Huang, Paolo Orsatti, Francesco Piazza. 67-70 [doi]
• 1 GHz programmable analog phase shifter for adaptive antennasMarcial Chua, Ken W. Martin. 71-74 [doi]
• A 10 mW inductorless, broadband CMOS low noise amplifier for 900 MHz wireless communicationsJohan Janssens, Jan Crols, Michiel Steyaert. 75-78 [doi]
• A 1.5 V, wide band 3 GHz, CMOS quadrature direct up-converter for multi-mode wireless communicationsMarc Borremans, Michiel Steyaert, Takashi Yoshitomi. 79-82 [doi]
• Integration architecture for system-on-a-chip designDrew Wingard, Alex Kurosawa. 85-88 [doi]
• Synthesis of interface controllers from timing diagram specificationsAbdelhalim El-Aboudi, El Mostapha Aboulhamid, Eduard Cerny. 89-92 [doi]
• On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rulePayman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl. 93-96 [doi]
• The virtual chip set: a parametric IP library for system-on-a-chip designEnrica Filippi, L. Licciardi, Archille Montanaro, Maurizio Paolini, Maura Turolla, M. Taliercio. 97-100 [doi]
• Complete mixed-signal building blocks for single-chip GSM baseband processingE. Liu, C. Wong, Q. Shami, S. Mohapatra, R. Landy, P. Sheldon, G. Woodward. 101-104 [doi]
• A novel CPLD based implementation of a motion detection algorithm for surveillance applicationsAli Benkhalil, Stanley S. Ipson, William Booth. 105-108 [doi]
• An energy conscious methodology for early design exploration of heterogeneous DSPsMarlene Wan, Yuji Ichikawa, David Lidsky, Jan M. Rabaey. 111-117 [doi]
• DSP16000: a high performance, low-power dual-MAC DSP core for communications applicationsM. Alidina, G. Burns, C. Holmqvist, E. Morgan, D. Rhodes, S. Simanapalli, M. Thierbach. 119-122 [doi]
• A single-chip low power DSP/RISC CPU with 0.25 /spl mu/m CMOS technologyTakashi Shikata, Shinya Kondou, Masanori Nose, Yoshio Kuniyasu, Mutsuhiro Naitoh, Hidetaka Suzuki. 123-126 [doi]
• A 9.5 mW 330 /spl mu/sec 1024-point FFT processorBevan M. Baas. 127-130 [doi]
• Design and implementation of a 1024-point pipeline FFT processorShousheng He, Mats Torkelson. 131-134 [doi]
• A 1 V, 25 /spl mu/W speech recognizer for portable systemsMichele Borgatti, Marco Felici, Alberto Ferrari, Roberto Guerrieri. 135-138 [doi]
• CMOS-year 2010 and beyond; from technological sideHiroshi Iwai. 141-148 [doi]
• Impact of high resolution lithography on IC mask designGraham Pugh, John Canning, Bernie Roman. 149-153 [doi]
• A new optimization strategy for CMOS device process in the era of 0.2 /spl mu/m and beyond for MPU's and ASIC'sKazutaka Mori, Ken'ichi Kikushima, Fumio Ootsuka, Shin'ichiro Mitani. 155-158 [doi]
• A merged 2.5 V and 3.3 V 0.25-/spl mu/m CMOS technology for ASICsIsik C. Kizilyalli, R. Huang, D. Hwang, H. Vaidya, Brittin Kane, Robert Ashton, S. Kuehne, X. Deng, M. Twiford, David Shuttleworth, E. Martin, X. Li, M. J. Thoma. 159-162 [doi]
• Laser formed connections for programmable wiringJoseph B. Bernstein, Wei Zhang, Carl H. Nicholas. 163-165 [doi]
• A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applicationsAtsuo Hanami, Stefan Scotzniovsky, Kazuya Ishihara, Tetsuya Matsumura, Shin'ichi Takeuchi, Haruyuki Ohkuma, Koji Nishigaki, Hirokazu Suzuki, Masahiro Kazayama, Toyohiko Yoshida, Koji Tsuchihashi. 169-172 [doi]
• Towards one chip HDTV MPEG2 encoder LSILi Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda. 173-176 [doi]
• An ultra low power variable length decoder for MPEG-2 exploiting codeword distributionSeong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan. 177-180 [doi]
• A system LSI utilizing media processor core "MMA"S. Kamijo, Y. Wakimoto, Tomio Satoh, A. Sakurai, E. Gotoh, M. Nakajima. 181-184 [doi]
• A single chip AV decoder for the DVD player adopting the MCP architectureR. Yamaguchi, A. Sota, M. Iwasa, M. Meiarashi, H. Ishii, M. Motohama, D. Kitamoto, T. Tanaka, T. Ochiai, K. Kimura, T. Kiyohara, Brent Wilson. 185-188 [doi]
• Architecture and implementation of a bitserial sorter for weighted median filteringChristiane Henning, Tobias G. Noll. 189-192 [doi]
• Implementation of H.324 audiovisual codec for mobile computingGen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Takao Onoye, Isao Shirakawa. 193-196 [doi]
• A simple algorithm for calculating frequency-dependent inductance boundsZhijiang He, Lawrence T. Pileggi. 199-202 [doi]
• Nonlinear macromodels of large coupled interconnect networksBruno Franzini, Cristiano Forzan, Davide Pandini, Y. Liu, Carlo Guardiani. 203-206 [doi]
• How to make theoretically passive reduced-order models passive in practiceZhaojun Bai, Peter Feldmann, Roland W. Freund. 207-210 [doi]
• Efficient full-wave simulation in layered, lossy mediaSharad Kapur, David E. Long, Jinsong Zhao. 211-214 [doi]
• Systematic calibration of AC MOSFET model parameters including non-quasi-static effectPaolo Miliozzi, Mishel Matloubian, Mark Tennyson. 215-217 [doi]
• High-frequency application of MOS compact models and their development for scalable RF model librariesDavid R. Pehlke, Michael Schroter, A. Burstein, Mishel Matloubian, M. Frank Chang. 219-222 [doi]
• Modified mismatch-shaping for continuous-time delta-sigma modulatorsTao Shui, Richard Schreier, Forrest Hudson. 225-228 [doi]
• A 13 bit, 1.4 MS/s, 3.3 V sigma-delta modulator for RF baseband channel applicationsArnold R. Feldman, Bernhard E. Boser, Paul R. Gray. 229-232 [doi]
• A 150 MHz 13b 12.5 mW IF digitizerSubhajit Sen, Bosco Leung. 233-236 [doi]
• A Nyquist rate pixel level ADC for CMOS image sensorsDavid X. D. Yang, Boyd Fowler, Abbas El Gamal. 237-240 [doi]
• Video-rate D/A converter using reduced rate sigma-delta modulationDagnachew Birru, Engel Roza. 241-244 [doi]
• A 325 MHz 3.3 V 10-bit CMOS D/A converter core with novel latching driver circuitNicholas van Bavel. 245-248 [doi]
• A 12 bit 200 MHz low glitch CMOS D/A converterAnne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas, Augusto Manuel Marques, José Bastos, Michiel Steyaert, Georges G. E. Gielen, Willy Sansen. 249-252 [doi]
• A low power, high performance, 960 macrocell, SRAM based complex PLDSchuyler Shimanek, Cesar Maldonado, Victor Ruybalid, Roy Darling. 255-260 [doi]
• Computational field programmable architectureAlireza Kaviani, Daniel Vranesic, Stephen Dean Brown. 261-264 [doi]
• A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capabilityDirk Reese, Eric Chun, Sammy Cheung, Edmond Lau, Michael Chu, Gwen Liang, Nghia Van Tran, Brad Vest, Richard Smolen, Minchang Liang, Seshan Sekariapuram, Behzad Nouban, Myron Wong, John Costello, John Turner. 265-268 [doi]
• Implementing logic in FPGA embedded memory arrays: architectural implicationsSteven J. E. Wilton. 269-272 [doi]
• A silicon efficient FLEX 6000 programmable logic architectureChiakang Sung, Richard Cliff, Joseph Huang, Bonnie Wang, Khai Nguyen, Xtaobao Wang, Kerry Veenstra, Bruce Pedersen, John Turner. 273-276 [doi]
• A current-mode based field programmable analog array architecture for signal processing applicationsX. Quan, Sherif H. K. Embabi, Edgar Sánchez-Sinencio. 277-280 [doi]
• Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low powerRichard C. Foss, J. Wu, J. Benzreba, G. Valcourt, P. Vlasenko, Y. Wang, Peter Gillingham. 283-286 [doi]
• A DRAM module generator with an expandable cell array schemeHideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata. 287-290 [doi]
• Hole filling: a novel delay reduction technique using selector logicShunzo Yamashita, Naoki Katoh, Yasuhiko Sasaki, Yohei Akita, Hidetoshi Chikata, Kazuo Yano. 291-294 [doi]
• Hierarchical watermarking in IC designEdoardo Charbon. 295-298 [doi]
• FPGA fingerprinting techniques for protecting intellectual propertyJohn C. Lach, William H. Mangione-Smith, Miodrag Potkonjak. 299-302 [doi]
• An overview of library characterization in semi-custom designBinay Ackalloor, Dinesh Gaitonde. 305-312 [doi]
• A new algorithm for computing the "effective capacitance" in deep sub-micron circuitsRobert Macys, Steven McCormick. 313-316 [doi]
• Timing qualification of a 0.25-/spl mu/m CMOS ASIC library using BSIM3 FET modelsDaniel Coops, Josef Watts, Charles Windisch Jr. 317-320 [doi]
• Manufacturability analysis of standard cell librariesHans T. Heineken, Jitendra Khare, Manuel d'Abreu. 321-324 [doi]
• A CMOS cell generation system for two-dimensional transistor placementSatoshi Shibatani, Toshiyuki Sadakane, Hiroomi Nakao, Masayuki Terai, Kaoru Okazaki. 325-328 [doi]
• Standard cell power IC designAndrew G. Marshall, Tom Schmidt, Bill Grose, Wayne Chen. 329-332 [doi]
• Design considerations for gigabit Ethernet 1000Base-T twisted pair transceiversMehdi Hatamian, Oscar E. Agazzi, John Creigh, Henry Samueli, Andrew J. Castellano, David Kruse, Avi Madisetti, Nariman Yousefi, Klaas Bult, Patrick Pai, Myles Wakayama, Mike M. McConnell, Marty Colombatt. 335-342 [doi]
• A 3.3 V analog adaptive line-equalizer for fast Ethernet data communicationJoseph N. Babanezhad. 343-346 [doi]
• A 10-Gbps 83 mW GaAs HBT equalizer/detector for coaxial cable channelsKeith T. Oshiro, Gregory T. Uehara, Aaron K. Oki, Ben Tang. 347-350 [doi]
• A dual-channel QAM/QPSK receiver IC with integrated cable set-top box functionalityLionel J. D'Luna, Paul Yang, Dean W. Mueller, Kelly B. Cameron, Huan-Chang Liu, David Gee, Fang Lu, Robert A. Hawley, Steve Tsubota, Charles Reames, Henry Samueli. 351-354 [doi]
• 1.5 watt 622/155 Mbps single chip for full ATM-SDH/SONET physical layer in 0.5 /spl mu/m BiCMOS 3.3 VMario Diu-Nava, Sergio Zocchi, Laurent Dugoujon, Didier Belot, Pierre Delerue, Sébastien Dedieu, Mourad Messaou. 355-358 [doi]
• A multistage amplifier topology with embedded tracking compensationRamsin M. Ziazadeh, Hiok-Tiaq Ng, David J. Allstot. 361-364 [doi]
• A 120 MHz, 12 mW CMOS current feedback opampKonstantinos Manetakis, Chris Toumazou, Christos Papavassiliou. 365-368 [doi]
• A CMOS instrumentation amplifier with 600 nV offset, 8.5 nV//spl radic/(Hz) noise and 150 dB CMRRChristian Menolfi, Qiuting Huang. 369-372 [doi]
• A 1.8 V pseudo-differential switched-capacitor amplifierZeki Sezgin Günay, Eric G. Soenen, Sherif H. K. Embabi, Edgar Sánchez-Sinencio. 373-376 [doi]
• A high-speed BiCMOS switched-current track-and-hold circuitTristan Reimann, François Krummenacher, Michel J. Declercq. 377-380 [doi]
• An open-loop full CMOS 103 MHz -61 dB THD S/H circuitKhayrollah Hadidi, Masahiro Sasaki, Tadatoshi Watanabe, Daigo Muramatsu, Takashi Matsumoto 0001. 381-383 [doi]
• Architectures and circuits for RF CMOS receiversBehzad Razavi. 393-400 [doi]
• A high Q 200 MHz low-power fully integrated bandpass IF filterDominique Morche, Denis Pache, Ernesto Perea, Patrice Senn. 401-404 [doi]
• A VLSI low power solution for mobile satellite radio receiversGiovanni Calí, Pietro Erratico, Massimo Gimignani, Piero Vita. 405-408 [doi]
• Silicon germanium and silicon bipolar RF circuits for 2.7 V single chip radio transceiver integrationJan Sevenhans, Bart Verstraeten, Graham Fletcher, Harry Dietrich, Winfried Rabe, Jean Luc Bacq, J. Varin, J. Dulongpont. 409-412 [doi]
• A 0.25 /spl mu/m CMOS transceiver front-end for GSMFrancesco Piazza, Paolo Orsatti, Qiuting Huang, T. Morimoto. 413-416 [doi]
• An automatic offset compensation technique applicable to existing operational amplifier core cellMaher Kayal, R. T. Lara Sáez, Michel J. Declercq. 419-422 [doi]
• A baseband integrated circuit for homodyne cordless phonesVittorio Comino, Dima Shulman, Susan J. Walker, Sanjay Kasturia, Michael E. Prise. 423-426 [doi]
• A 3-V high-bandwidth integrator for magnetic disk read channel continuous-time filtering applicationsYong Wang, Gregory T. Uehara, Min Ren. 427-430 [doi]
• Ferroelectric nonvolatile memories for embedded applicationsRobert E. Jones. 431-438 [doi]
• An embedded FeRAM macro cell for a smart card microcontrollerTohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Oliizaki, Yoichi Miyasalca, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima. 439-442 [doi]
• Modeling and simulation for low power in mixed-signal integrated systemsGeorges G. E. Gielen. 445-449 [doi]
• MPDE methods for efficient analysis of wireless systemsJaijeet Roychowdhury. 451-454 [doi]
• Practical timing analysis of asynchronous circuits using time separation of eventsSupratik Chakraborty, Kenneth Y. Yun, David L. Dill. 455-458 [doi]
• Simulator for switched-current integrated circuitsI. Yusim, G. Ionis, Ken Suyama. 459-462 [doi]
• Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuitsC.-J. Richard Shi, Xiang-Dong Tan. 463-466 [doi]
• Transforming small-signal modeling into control system modelingFrancky Leyn, Willy Sansen, Georges G. E. Gielen. 469-472 [doi]
• Behavioral model for D/A converters as VSI virtual componentsJan Vandenbussche, Geert Van der Plas, Georges G. E. Gielen, Michiel Steyaert, Willy Sansen. 473-476 [doi]
• Automated design of switched-current cellsIan O'Connor, Andreas Kaiser. 477-480 [doi]
• Schematic driven module generation for analog circuits with performance optimization and matching considerationsRavindranath Naiknaware, Terri S. Fiez. 481-484 [doi]
• Mondriaan: a tool for automated layout synthesis of array-type analog blocksGeert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy Sansen. 485-488 [doi]
• Oscillator jitter due to supply and substrate noiseFrank Herzel, Behzad Razavi. 489-492 [doi]
• A top-down low power design technique using clustered voltage scaling with variable supply-voltage schemeMototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda. 495-498 [doi]
• A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniquesRam Krishnamurthy 0001, Herman Schmit, L. Richard Carley. 499-502 [doi]
• A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]Thierry Melly, Alain-Serge Porret, Christian C. Enz, Maher Kayal. 503-506 [doi]
• Estimation of average switching power under accurate modeling of signal correlationsZhanping Chen, Kaushik Roy 0001, Yibin Ye. 507-510 [doi]
• The direct skew detect synchronous mirror delay (Direct SMD) for ASICsTakanori Saeki, Koichiro Minami, Hiroshi Yoshida, Hisamitsu Suzuki. 511-514 [doi]
• VCOs with very low sensitivity to noise on the power supplyKamran Iravani, Gary Miller. 515-518 [doi]
• Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testabilityWei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel. 519-522 [doi]
• Design in hot-carrier reliability for high performance logic applicationsPeng Fang, Jiang Tao, Jone F. Chen, Chenming Hu. 525-531 [doi]
• Performance and reliability of asymmetric LDD devices and logic gatesJone F. Chen, Jiang Tao, Peng Fang, Chenming Hu. 533-536 [doi]
• Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technologyMing-Dou Ker, Jeng-Jie Peng. 537-540 [doi]
• Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protectionMing-Dou Ker, Hun-Hsien Chang. 541-544 [doi]
• Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]Shyh-Jye Jou, Wei-Chung Cheng, Yu-Tao Lin. 545-548 [doi]
• On-chip analog signal generator for mixed-signal built-in self-testBenoit Dufort, Gordon W. Roberts. 549-552 [doi]
• RF-CMOS oscillators with switched tuningA. Kral, Farbod Behbahani, Asad A. Abidi. 555-558 [doi]
• A 2.7 V 900 MHz/1.9 GHz dual-band transceiver IC for digital wireless communicationJoo Leong Tham, Mihai A. Margarit, Bernd Prégardier, Chris Hull 0001, Rahul Magoon, Frank Carr. 559-562 [doi]
• A 2 V 1.6 GHz BJT phase-locked loopWei-Zen Chen, Jieh-Tsorng Wu. 563-566 [doi]
• A 1 GHz, low-phase-noise CMOS frequency synthesizer with integrated LC VCO for wireless communicationsByeong-ha Park, Phillip E. Allen. 567-570 [doi]
• A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communicationsSteve Lo, Christian Olgaard, Dennis Rose. 571-574 [doi]
• 2.488 Gb/s silicon bipolar clock and data recovery IC for SONET (OC-48)German Gutierrez, Shyang Kong, Bruce Coy. 575-578 [doi]
• Issues for fabless design companies moving towards deep submicron system on a chip designW. Terry Coston. 581-587 [doi]
• Reducing switching activity on datapath buses with control-signal gatingHema Kapadia, Giovanni De Micheli, Luca Benini. 589-592 [doi]
• A new direction in ASIC high-performance clock methodologyKeith M. Carrig, Niel T. Gargiulo, Roger P. Gregor, Daniel R. Menard, Harold E. Reindel. 593-596 [doi]
• A nonlinear programming and local improvement method for standard cell placementYamin Du, Anthony Vannelli. 597-600 [doi]
• A new router for reducing "antenna effect" in ASIC designHiroshi Shirota, Toshiyuki Sadakane, Masayuki Terai, Kaoru Okazaki. 601-604 [doi]
• Combined transistor sizing with buffer insertion for timing optimizationYanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim. 605-608 [doi]