Kazutaka Mori - researchr alias

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Viewing Publication 1 - 4 from 4

2014

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control TechniqueYukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa. tvlsi, 22(3):575-584, 2014. [doi]

2001

Design methodology of high performance microprocessor using ultra-low threshold voltage CMOSTamotsu Miyake, Takeo Yamashita, Norikatsu Asari, Hideki Sekisaka, Tom Sakai, Kazuhiro Matsuura, Atsushi Wakahara, Hideyuki Takahashi, Tom Hiyama, Kazuhisa Miyamoto, Kazutaka Mori. cicc 2001: 275-278 [doi]

1998

TCAD/DA for MPU and ASIC DevelopmentHiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori. aspdac 1998: 129-134

A new optimization strategy for CMOS device process in the era of 0.2 /spl mu/m and beyond for MPU's and ASIC'sKazutaka Mori, Ken'ichi Kikushima, Fumio Ootsuka, Shin'ichiro Mitani. cicc 1998: 155-158 [doi]

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