Table of Contents

• An anti-blocker structure MOSFET-C filter for a direct conversion receiverAtsushi Yoshizawa, Yannis P. Tsividis. 5-8 [doi]
• A 2.7 V CMOS GSM/WCDMA continuous-time filter with automatic tuningSaska Lindfors, Tuomas Hollman, Teemu Salo, Kari Halonen. 9-12 [doi]
• Embedded anti-aliasing in switched-capacitor ladder filtersDaniel Senderowicz, Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto. 13-16 [doi]
• 1.5 V 5.0 MHz switched capacitor circuits in 1.2 μm CMOS without voltage bootstrapperLei Wang, S. H. K. Embabi, Edgar Sanchez-Sinencio. 17-20 [doi]
• A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiverJorge Grilo, Ian Galton, Kevin Wang 0004, Raymond Montemayor. 23-26 [doi]
• A 105 dB SNR multibit ΣΔ ADC for digital audio applicationsKhiem Nguyen, Bob Adams 0001, Karl Sweetland. 27-30 [doi]
• A 1.8 V ΔΣ modulator interface for electret microphone with on-chip referenceOvidiu Bajdechi, Johan H. Huijsing. 31-34 [doi]
• Ultra low voltage switched opamp ΣΔ modulator for portable applicationsJens Sauerbrey, Roland Thewes. 35-38 [doi]
• ESD protection device issues for IC designsCharvaka Duvvury. 41-48 [doi]
• An IF CMOS signal component separator chip for LINC transmittersBo Shi, Lars Sundström. 49-52 [doi]
• Accurate prediction of spectral regrowth and in-channel distortion based on CDMA signal time-domain modelVladimir Aparin. 53-56 [doi]
• A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifierIchiro Aoki, Scott D. Kee, David B. Rutledge, Ali Hajimiri. 57-60 [doi]
• Programmable logic IP cores in SoC design: opportunities and challengesSteven J. E. Wilton, Resve Saleh. 63-66 [doi]
• PLC advanced technology demonstrator TestChipBTheodore Vaida. 67-70 [doi]
• A hardware/software solution for embeddable FPGAFrank Lien, Jason Feng, Eddy Huang, Chung Sun, Tong Liu, Naihui Liao, David Hightower. 71-74 [doi]
• A novel FPGA architecture supporting wide shallow memoriesSteven W. Oldridge, Steven J. E. Wilton. 75-78 [doi]
• Platform design approach for re-configurable network appliancesRadim Cmar, Robert Pasko, Jean-Yves Mignolet, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde. 79-82 [doi]
• Mixed-swing methodology for domino logic circuitsAshoke Rave, L. Rick Carley. 85-88 [doi]
• Utilizing surplus timing for power reductionMototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda. 89-92 [doi]
• TH-hopping scheme for 82% power saving in low-voltage processorsKoichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai. 93-96 [doi]
• Design of an analogue ASIC using subthreshold CMOS transistors to model biological neuronsLudovic Alvado, Jean Tomas, Sylvie Renaud-Le Masson, Vincent Douence. 97-100 [doi]
• A 40 μA/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implantsWim Claes, Willy Sansen, Robert Puers. 101-104 [doi]
• High sensitivity silicon magnetic field detectorJohn Doyle. 105-108 [doi]
• Interface circuit for metal-oxide gas sensorPierre-François Ruedi, Pascal Heim, Alessandro Mortara, Edoardo Franzi, Henri Oguey, Xavier Arreguit. 109-112 [doi]
• A 800 mW, full-rate ADSL-RT analog frontend IC with integrated line driverHubert Weinberger, Andreas Wiesbauer, Christian Fleischhacker, Joerg Hauptmann. 115-118 [doi]
• A 12-bit integrated analog front-end for broadband wireline networksIuri Mehr, Prabir C. Maulik, Donald Paterson. 119-122 [doi]
• A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOSDavid J. Foley, Michael P. Flynn. 123-126 [doi]
• A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibreM. Altmann, J. M. Caia, R. Morle, Michael Dunsmore, Y. Xie, Namik Kocaman. 127-130 [doi]
• A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wireTai-Cheng Lee, Behzad Razavi. 131-134 [doi]
• A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technologyScott D. Huss, Mark Mullen, C. Thomas Gray, Randall Smith, Mark Summers, Jeff Shafer, Pat Heron, Tim Sawinska, Joe Medero. 135-138 [doi]
• Design techniques for very low power ADCsRobert C. Taft, Maria Rosaria Tursi, Andrew Glenny. 141-144 [doi]
• A `digital' 6-bit ADC in 0.25 μm CMOSConor Donovan, Michael P. Flynn. 145-148 [doi]
• A 900 MS/s 6b interleaved CMOS flash ADCBaiying Yu, William C. Black Jr.. 149-152 [doi]
• A 165 MS/s 8-bit CMOS A/D converter with background offset cancellationGennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan. 153-156 [doi]
• A low power, 10-bit CMOS D/A converter for high speed applicationsMarc Borremans 0001, Anne Van den Bosch, Michiel Steyaert, Willy Sansen. 157-160 [doi]
• A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THDMohsen Moussavi, Ralph Mason, Calvin Plett. 161-164 [doi]
• A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converterJiandong Jiang, Edward K. F. Lee. 165-168 [doi]
• FeRAM device and circuit technologies fully compatible with advanced CMOSHideo Toyoshima, Sota Kobayashi, Junichi Yamada, Tohru Miwa, Hiroki Koike, Hidenori Takeuchi, Hidemitsu Mori, Naoki Kasai, Yukihiko Maejima, Nobuhira Tanabe, Toru Tatsumi, Hiromitsu Hada. 171-178 [doi]
• CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chipShoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi. 179-182 [doi]
• An ASIC-embedded content addressable memory with power-saving and design for test featuresThomas Chadwick, Tar1 Gordon, Rahul Nadkarni, Jeremy Rowland. 183-186 [doi]
• A shared built-in self-repair analysis for multiple embedded memoriesJun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka. 187-190 [doi]
• Shared fuse macro for multiple embedded memory devices with redundancyMichael R. Ouellette, Darren Anand, Peter Jakobsen. 191-194 [doi]
• A 2.2 GHz CMOS VCO with inductive degeneration noise suppressionPietro Andreani, Henrik Sjöland. 197-200 [doi]
• A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applicationsCarlo Samori, Salvatore Levantino, Vito Boccuzzi. 201-204 [doi]
• Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCOSeong-Mo Yim, Kenneth K. O. 205-208 [doi]
• Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCOAlfio Zanchi, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita. 209-212 [doi]
• A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCOKoichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina. 213-216 [doi]
• A CMOS VLSI delay oriented waveform converter dedicated to the synthesizer of an UMTS transceiverAnne Spataro, Yann Deval, Jean-Baptiste Bigueret, Pascal Fouillat, Didier Belot. 217-220 [doi]
• Modeling and analysis of manufacturing variationsSani R. Nassif. 223-228 [doi]
• Impact of within-die parameter fluctuations on future maximum clock frequency distributionsKeith A. Bowman, James D. Meindl. 229-232 [doi]
• Effects of non-uniform substrate temperature on the clock signal integrity in high performance designsAmir H. Ajami, Massoud Pedram, Kaustav Banerjee. 233-236 [doi]
• R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chipHoward H. Smith, Aline Deutsch, Sharad Mehrotra, David Widiger, Michael A. Bowen, Allan H. Dansky, Gerard V. Kopcsay, Byron Krauter. 237-240 [doi]
• A fast analytical technique for estimating the bounds of on-chip clock wire inductanceYi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton. 241-244 [doi]
• Circuit-aware on-chip inductance extractionHaitian Hu, Sachin S. Sapatnekar. 245-248 [doi]
• Circuits for on-chip sub-nanosecond signal capture and characterizationNazmy Abaskharoun, Gordon W. Roberts. 251-254 [doi]
• Effect of RTL coding style on testabilityYu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy. 255-258 [doi]
• A deterministic scan-BIST architecture with application to field testing of high-availability systemsShivakumar Swaminathan, Krishnendu Chakrabarty. 259-262 [doi]
• Low-cost, software-based self-test methodologies for performance faults in processor control subsystemsSobeeh Almukhaizim, Peter Petrov, Alex Orailoglu. 263-266 [doi]
• An efficient method of applying hot-carrier reliability simulation to logic designHisuko Sato, Mariko Ohtsuka, Kazumasa Yanagisawa, Peter M. Lee. 267-270 [doi]
• Design for manufacturability characterization and optimization of mixed-signal IPPatrick McNamara, Sharad Saxena, Carlo Guardiani, Hideki Taguchi, Emiko Yoshida, Naoki Takahashi, Koji Miyamoto, Kenichi Sugawara, Takeshi Matsunaga. 271-274 [doi]
• Design methodology of high performance microprocessor using ultra-low threshold voltage CMOSTamotsu Miyake, Takeo Yamashita, Norikatsu Asari, Hideki Sekisaka, Tom Sakai, Kazuhiro Matsuura, Atsushi Wakahara, Hideyuki Takahashi, Tom Hiyama, Kazuhisa Miyamoto, Kazutaka Mori. 275-278 [doi]
• DSP techniques for optical transceiversKamran Azadet, Erich Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Mike Shaffer, Leilei Song, Meng-Lin Yu. 281-288 [doi]
• Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoderKatsutoshi Seki, Kousuke Mikami, M. Baba, N. Shinohara, S. Suzuki, H. Tezuka, S. Uchino, N. Okada, Y. Kakinuma, A. Katayama. 289-292 [doi]
• A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoderChris J. Howland, Andrew J. Blanksby. 293-296 [doi]
• Implementation of a Hermitian decoder IC in 0.35 μm CMOSJonathan B. Ashbrook, Naresh R. Shanbhag, Ralf Koetter, Richard E. Blahut. 297-300 [doi]
• A multicarrier QAM-modulator for WCDMA basestation with on-chip D/A converterMarko Kosunen, Jouko Vankka, Mikko Waltari, Kari Halonen. 301-304 [doi]
• A platform-based highly parallel digital signal processorThomas Richter, Wolfram Drescher, Frank Engel, S. Kobayashi, Vladimir Nikolajevic, Matthias Weiss, Gerhard P. Fettweis. 305-308 [doi]
• A low-power digital filter IC via soft DSPRajamohana Hegde, Naresh R. Shanbhag. 309-312 [doi]
• Design of high-speed circuits for optical communication systemsBehzad Razavi. 315-322 [doi]
• A 9.8-11.5 GHz quadrature ring oscillator for optical receiversJohan van der Tang, Dieter Kasperkovitz, Arthur H. M. van Roermund. 323-326 [doi]
• A 1.0 V GHz range 0.13 μm CMOS frequency synthesizerLizhong Sun, Dale Nelson. 327-330 [doi]
• Circuits and technologies for highly integrated optical networking ICs at 10 Gb/s to 40 Gb/sSorin P. Voinigescu, P. Popescu, P. Banens, Miles Copeland, G. Fortier, K. Howlett, M. Herod, David Marchesan, Jonathan L. Showell, S. Sziiagyi, Hai Tran, J. Weng. 331-338 [doi]
• Speed-power-accuracy trade-off in high-speed ADCs: what about nano-electronics?Koen Uyttenhove, Michiel Steyaert. 341-344 [doi]
• Autocorrelation analysis of distortion generated from bandpass nonlinear circuitsKevin G. Gard, Lawrence E. Larson, Michael B. Steer. 345-348 [doi]
• Dedicated system-level simulation of ΔΣ modulatorsKenneth Francken, Martin Vogels, Georges G. E. Gielen. 349-352 [doi]
• Behavioral modeling for timing, noise, and signal integrity analysisJerry D. Hayes, Larry Wissel. 353-356 [doi]
• Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliabilityShizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama. 357-360 [doi]
• A fast method for identifying matching-relevant transistor pairsFrank Schenkel, Michael Pronath, Helmut Graeb, Kurt Antreich. 361-364 [doi]
• Capacity limits and matching properties of lateral flux integrated capacitorsRoberto Aparicio, Ali Hajimiri. 365-368 [doi]
• When do we need non-quasistatic CMOS RF-models?Elmar Gondro, Oskar Kowarik, Gerhard Knoblinger, Peter Klein. 377-380 [doi]
• Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOSHajime Nakayama, Pin Su, Chenming Hu, Motoaki Nakamura, Hiroshi Komatsu, Kaneyoshi Takeshita, Yasutoshi Komatsu. 381-384 [doi]
• Comparative low frequency noise analysis of bipolar and MOS transistors using an advanced complementary BiCMOS technologyJeffrey A. Babcock, Bill Loftin, Praful Madhani, Xinfen Chen, Angelo Pinto, Dieter K. Schroder. 385-388 [doi]
• A new analytical model for high frequency MOSFET noiseSimona Donati Guerrieri, Fabrizio Bonani, Giovanni Ghione, Muhammad Ashraful Alam. 389-392 [doi]
• Experimental study on MOSFET's flicker noise under switching conditions and modelling in RF applicationsZhaofeng Zhang, Jack Lau. 393-396 [doi]
• A new dynamic, self-consistent electro-thermal model of power HBTs and a novel interpretation of thermal collapse loci in multi-finger devicesFederica Cappelluti, Fabrizio Bonani, Simona Donati Guerrieri, Giovanni Ghione, Marco Peroni, Antonio Cetronio, R. Graffitti. 397-400 [doi]
• Modeling of monolithic lumped planar transformers up to 20 GHzDaniel Kehrer, Werner Simbürger, Hans-Dieter Wohlmuth, Arpad L. Scholtz. 401-404 [doi]
• Successful modular process technology for system-on-a-chip applicationsWilliam T. Cochran. 407-412 [doi]
• A system-on-chip for pressure-sensitive fabricMaximilian Sergio, Nicolò Manaresi, Marco Tartagni, Roberto Canegallo, Roberto Guerrieri. 413-416 [doi]
• A single chip terminal solution for high-end telephone applicationsVinod Nair, Martin Erdmann, Shridhar Mubaraq Mishra, Juraj Povazanec, Amit Shaligram, Chun Feng Hu. 417-420 [doi]
• A one chip super graphics CPU with direct unified memory controller suitable for car information and control systemYasuhiro Nakatsuka, Tetsuya Shhomura, Yuichiro Morita, Kazuhisa Takami, Manabu Joh, Masahisa Narita, Kazushige Yamagishi, Yutaka Okada, Jun Satoh. 421-423 [doi]
• 2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder systemSatoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Yusuke Kanehira, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuva Matsumura. 425-428 [doi]
• The first near zero-IF RX, 2-point modulation TX CMOS SOC Bluetooth solutionChristian Duerdodt, Martin Friedrich, Christian Grewing, Markus Hammes, Andre Hanke, Stefan Heinen, Jürgen Oehm, Duyen Pham-Stabner, Dietolf Seippel, Detlev Theil, Stefan van Waasen. 429-432 [doi]
• C++ based system design of a 72 Mb/s OFDM transceiver for wireless LANDiederik Verkest, Wolfgang Eberle, Patrick Schaumont, Bert Gyselinckx, Serge Vemalde. 433-439 [doi]
• Behavioral modeling of analog and mixed signal IC's: case studies of analog circuit simulation beyond SPICEAsad A. Abidi. 443-450 [doi]
• A SOI-BiCMOS 800 Mbps write driver for hard disk drivesN. Fujii, M. Kuraishi, T. Mochizuki, S. Irikuraz, T. Hirose. 451-454 [doi]
• A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communicationsBahram Zand, Khoman Phang, David A. Johns. 455-458 [doi]
• A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHzUma Chilakapati, Terri S. Fiez, Aria Eshraghi. 459-462 [doi]
• Band-gap references for near 1-V operation in standard CMOS technologyAndrea Pierazzi, Andrea Boni, Carlo Morandi. 463-466 [doi]
• A 0.9 V, 0.51 μA rail-to-rail CMOS operational amplifierTroy Stockstad, Hirokazu Yoshizawa. 467-470 [doi]
• Coherent functional, electrical and physical modeling of IP blocks using ALFWolfgang Roethig. 473-480 [doi]
• Clock generator using factorial DLL for video applicationsJean-Baptiste Bégueret, Yann Deval, Olivier Mazouffre, Anne Spataro, Pascal Fouillat, Eric Benoit, Jean Mendoza. 485-488 [doi]
• A fast-lock mixed-mode DLL using a 2-b SAR algorithmGuang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu. 489-492 [doi]
• An ESD protection circuit for mixed-signal ICsHaigang Feng, Ke Gong, Albert Z. Wang. 493-496 [doi]
• 7V tristate-capable output buffer implemented in standard 2.5 V CMOS processVladimir I. Prodanov, Vito Boccuzzi. 497-500 [doi]
• Shared data line technique for doubling the data transfer rate per pin of differential interfacesFumitoshi Hatori, Shouhei Kousai, Yasuo Unekawa. 501-504 [doi]
• A 2 GB/s high speed link with differential simultaneous bi-directional IODelbert Cecchi, Charles Hanson, Curtis Preuss. 505-508 [doi]
• Solutions for highly integrated future generation software radio basestation transceiversArmin Splett, Hans-Joachim Dreßler, Armin Fuchs, Ralf Hofmann, Björn Jelonnek, Helmut Kling, Eric Koenig, Anton Schultheiß. 511-518 [doi]
• An integrated RF transceiver for DECT applicationSalvatore Cosentino, Pietro Filoramo, Angelo Granata, Marco Marletta, Giuseppe Martino, Roberto Pelleriti, Felice Torrisi, Mario Paparo, Gaetano Cosentino, Paolo Vita, Giuseppe Palmisano. 519-522 [doi]
• An IF FSK demodulator for Bluetooth in 0.35 μm CMOSHooman Darabi, Shahla Khorram, Brima Ibrahim, Maryam Rofougaran, Ahmadreza Rofougaran. 523-526 [doi]
• A 900 MHz, 0.9 V low-power CMOS downconversion mixerCarl J. Debono, Franco Maloberti, J. Micaller. 527-530 [doi]
• A comparison of CMOS and SiGe LNA's and mixers for wireless LAN applicationXi Li, Tom Brogan, Mark Esposito, Brent Myers, Kenneth K. O. 531-534 [doi]
• Interface socket design methodology to generate embedded DRAM macrosRyo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano. 537-540 [doi]
• A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applicationsThomas E. Bonnerud, Bjørnar Hernes, Trond Ytterdal. 541-544 [doi]
• A design environment for high throughput, low power dedicated signal processing systemsW. Rhett Davis, Ning Zhang, Kevin Camera, Fred Chen, Dejan Markovic, Nathan Chan, Borivoje Nikolic, Robert W. Brodersen. 545-548 [doi]
• RTL morphing: making IP-reuse work in system-on-a-chip designsShunzo Yamashita, Hidetoshi Chikata, Yuji Onishi, Naoki Kato, Tom Hiyama, Kazuo Yano. 549-552 [doi]
• Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systemsYoungsoo Shin, Hiroshi Kawaguchi, Takayasu Sakurai. 553-556 [doi]
• Silicon-germanium BiCMOS technology and a CAD environment for 2-40 GHz VLSI mixed-signal ICsSeshadri Subbanna, L. Larson, Greg G. Freeman, David Ahlgren, Kenneth J. Stein, Carl E. Dickey, James Mecke, A. Rincon, P. Bacon, Robert A. Groves, Mehmet Soyuer, David L. Harame, James S. Dunn, D. Rowe, W. Chon, Dean A. Herman Jr., Bernard S. Meyerson. 559-566 [doi]
• A 10 GHz SiGe BiCMOS phase-locked-loop frequency synthesizerBernd-Ulrich H. Klepser, Markus Scholz, Wolfgang Klein. 567-570 [doi]
• Driving CMOS into the wireless communications arena with technology scalingKok Wai Johnny Chew, Shao-Fu Sanford Chu, Che Choi Chester Leung. 571-574 [doi]
• A completely integrated 2 GHz VCO with post-processed Cu inductorsJohn W. M. Rogers, Vladislav Levenets, Chris A. Pawlowicz, N. Garry Tarr, Tom J. Smy, Calvin Plett. 575-578 [doi]
• Micromachined high-Q inductors in 0.18 μm Cu interconnect low-K CMOSHasnain Lakdawala, Xu Zhu, Hao Luo, Suresh Santhanam, L. Rick Carley, Gary K. Fedder. 579-582 [doi]