Hiroki Koike - researchr alias

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Viewing Publication 1 - 24 from 24

2022

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error ReliabilityK. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda, Takamitsu Shinada, Hiroki Koike, Tetsuo Endoh, T. Makino, Takeshi Ohshima. irps 2022: 54-1 [doi]

2019

Cyclic groups are CI-groups for balanced configurationsHiroki Koike, István Kovács, Dragan Marusic, Mikhail E. Muzychuk. dcc, 87(6):1227-1235, 2019. [doi]

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT ApplicationsMasanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu. jssc, 54(11):2991-3004, 2019. [doi]

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHzMasanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu. isscc 2019: 202-204 [doi]

A novel memory test system with an electromagnet for STT-MRAM testingR. Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Soshi Sato. nvmts 2019: 1-4 [doi]

2018

Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test systemR. Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh. nvmts 2018: 1-5 [doi]

2017

Flag Bicolorings, Pseudo-Orientations, and Double Covers of MapsHiroki Koike, Daniel Pellicer, Miguel Raggi, Steve Wilson. combinatorics, 24(1):1, 2017. [doi]

2016

2014

Isomorphic tetravalent cyclic Haar graphsHiroki Koike, István Kovács. arsmc, 7(1):215-235, 2014. [doi]

2013

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating SchemeTakashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh. jssc, 48(6):1511-1520, June 2013. [doi]

2012

2011

An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/OHiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura. ieicet, 94-C(6):945-952, 2011. [doi]

2010

An electrically adjustable 3-terminal regulator with post-fabrication level-trimming functionHiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura. aspdac 2010: 365-366 [doi]

2002

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollersJunichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio. jssc, 37(8):1073-1079, 2002. [doi]

2001

2000

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitorsTohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio. cicc 2000: 65-68 [doi]

1998

An embedded FeRAM macro cell for a smart card microcontrollerTohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Oliizaki, Yoichi Miyasalca, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima. cicc 1998: 439-442 [doi]

1992

1990

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