Table of Contents

• A PUF design for secure FPGA-based embedded systemsJason Helge Anderson. 1-6 [doi]
• Adaptive power management for real-time event streamsKai Huang, Luca Santinelli, Jian-Jia Chen, Lothar Thiele, Giorgio C. Buttazzo. 7-12 [doi]
• An alternative polychronous model and synthesis methodology for model-driven embedded softwareBijoy A. Jose, Sandeep K. Shukla. 13-18 [doi]
• Trace-based performance analysis framework for heterogeneous multicore systemsShih-Hao Hung, Chia-Heng Tu, Thean-Siew Soon. 19-24 [doi]
• Efficient model reduction of interconnects via double gramians approximationBoyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai. 25-30 [doi]
• Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling methodHai Wang, Sheldon X.-D. Tan, Gengsheng Chen. 31-36 [doi]
• VISA: versatile impulse structure approximation for time-domain linear macromodelingChi-Un Lei, Ngai Wong. 37-42 [doi]
• An extension of the generalized Hamiltonian method to ::::S::::-parameter descriptor systemsZheng Zhang, Ngai Wong. 43-47 [doi]
• Simultaneous slack budgeting and retiming for synchronous circuits optimizationShenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang. 49-54 [doi]
• A fast SPFD-based rewiring techniquePongstorn Maidee, Kia Bazargan. 55-60 [doi]
• iRetILP: an efficient incremental algorithm for min-period retiming under general delay modelDebasish Das, Jia Wang, Hai Zhou. 61-67 [doi]
• Room-temperature fuel cells and their integration into portable and embedded systemsNaehyuck Chang, Jueun Seo, Donghwa Shin, Younghyun Kim. 69-74 [doi]
• Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU designHui Shao, Chi-Ying Tsui, Wing-Hung Ki. 75-80 [doi]
• Dynamic power management in environmentally powered systemsClemens Moser, Jian-Jia Chen, Lothar Thiele. 81-88 [doi]
• Micro-scale energy harvesting: a system design perspectiveChao Lu, Vijay Raghunathan, Kaushik Roy. 89-94 [doi]
• Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memoryYi He, Chun Jason Xue, Cathy Qun Xu, Edwin Hsing-Mean Sha. 95-100 [doi]
• A new compilation technique for SIMD code generation across basic block boundariesHiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai. 101-106 [doi]
• LibGALS: a library for GALS systems design and modelingWei-Tsun Sun, Zoran Salcic, Avinash Malik. 107-112 [doi]
• Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banksTiantian Liu, Minming Li, Chun Jason Xue. 113-118 [doi]
• On-chip power network optimization with decoupling capacitors and controlled-ESRsWanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng. 119-124 [doi]
• An adaptive parallel flow for power distribution network simulation using discrete Fourier transformXiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng. 125-130 [doi]
• Technique for controlling power-mode transition noise in distributed sleep transistor networkYongho Lee, Taewhan Kim. 131-136 [doi]
• A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary conditionShuichi Aono, Masaki Unno, Hideki Asai. 137-141 [doi]
• Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and schedulingKuen-Huei Lin, Siao-Jie Cai, Chung-Yang (Ric) Huang. 143-148 [doi]
• SCGPSim: a fast SystemC simulator on GPUsMahesh Nanjundappa, Hiren D. Patel, Bijoy A. Jose, Sandeep K. Shukla. 149-154 [doi]
• A flexible hybrid simulation platform targeting multiple configurable processors SoCHao Shen, Frédéric Pétrot. 155-160 [doi]
• A fast heuristic scheduling algorithm for periodic ConcurrenC modelsWeiwei Chen, Rainer Dömer. 161-166 [doi]
• Design of networks on chips for 3D ICsSrinivasan Murali, Luca Benini, Giovanni De Micheli. 167-168 [doi]
• Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesisPaul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang 0002. 169-174 [doi]
• Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICsXin Zhao, Sung Kyu Lim. 175-180 [doi]
• A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V::::::DD:::::: applicationsJ. Singh, Krishnan Ramakrishnan, S. Mookerjea, S. Datta, Narayanan Vijaykrishnan, D. K. Pradhan. 181-186 [doi]
• CAD reference flow for 3D via-last integrated circuitsChang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu. 187-192 [doi]
• Energy and performance driven circuit design for emerging phase-change memoryDimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie. 193-198 [doi]
• Current source modeling in the presence of body biasSaket Gupta, Sachin S. Sapatnekar. 199-204 [doi]
• Manifold construction and parameterization for nonlinear manifold-based model reductionChenjie Gu, Jaijeet S. Roychowdhury. 205-210 [doi]
• A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodelHao Yu, Xuexin Liu, Hai Wang, Sheldon X.-D. Tan. 211-216 [doi]
• Formal verification of tunnel diode oscillator with temperature variationsKusum Lata, H. S. Jamadagni. 217-222 [doi]
• Constrained global scheduling of streaming applications on MPSoCsJun Zhu, Ingo Sander, Axel Jantsch. 223-228 [doi]
• Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processorsJungseob Lee, Shi-Ting Zhou, Nam Sung Kim. 229-234 [doi]
• Source-level timing annotation for fast and accurate TLM computation model generationKai-Li Lin, Chen Kang Lo, Ren-Song Tsay. 235-240 [doi]
• Improved on-chip router analytical power and area modelingAndrew B. Kahng, Bill Lin, Kambiz Samadi. 241-246 [doi]
• Data learning based diagnosisLi-C. Wang. 247-254 [doi]
• Post-silicon debugging for multi-core designsValeria Bertacco. 255-258 [doi]
• Low-cost design for repair with circuit partitioningKyungHo Kim, Byungtae Kang, Donghyun Kim, Sungchul Lee, Juyong Shin, Hyunchul Shin. 259-261 [doi]
• On signal tracing in post-silicon validationQiang Xu, Xiao Liu. 262-267 [doi]
• CrossRouter: a droplet router for cross-referencing digital microfluidic biochipsZigang Xiao, Evangeline F. Y. Young. 269-274 [doi]
• Optimal simultaneous pin assignment and escape routing for dense PCBsHui Kong, Tan Yan, Martin D. F. Wong. 275-280 [doi]
• CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstaclesYukihide Kohira, Atsushi Takahashi. 281-286 [doi]
• Obstacle-aware longest path using rectangular pattern detouring in routing gridsJin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen. 287-292 [doi]
• A performance-constrained template-based layout retargeting algorithm for analog integrated circuitsZheng Liu, Lihong Zhang. 293-298 [doi]
• Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layoutsRui He, Lihong Zhang. 299-304 [doi]
• Regularity-oriented analog placement with diffusion sharing and well island generationShigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki. 305-311 [doi]
• A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injectionJi Hwan (Paul) Chun, Jae-Wook Lee, Jacob A. Abraham. 312-317 [doi]
• Technology mapping with crosstalk noise avoidanceFang-Yu Fan, Hung-Ming Chen, I-Min Liu. 319-324 [doi]
• Fault-tolerant resynthesis with dual-output LUTsJu-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li. 325-330 [doi]
• TRECO: dynamic technology remapping for timing engineering change ordersKuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang. 331-336 [doi]
• Multi-operand adder synthesis on FPGAs using generalized parallel countersTaeko Matsunaga, Shinji Kimura, Yusuke Matsunaga. 337-342 [doi]
• Checker-pattern and shared two pixels LOFIC CMOS image sensorsYoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigetoshi Sugawa. 343-344 [doi]
• A CMOS image sensor with 2.0-e:::-::: random noise and 110-ke:::-::: full well capacity using column source follower readout circuitsTakahiro Kohara, Woonghee Lee, Koichi Mizobuchi, Shigetoshi Sugawa. 345-346 [doi]
• Checkered white-RGB color LOFIC CMOS image sensorShun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa. 347-348 [doi]
• A versatile recognition processor for sensor network applicationsRisako Takashima, Yuya Hanai, Yuichi Hori, Tadahiro Kuroda. 349-350 [doi]
• A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmittersDaisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa. 351-352 [doi]
• An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC developmentLiang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang. 353-354 [doi]
• Cascaded time difference amplifier using differential logic delay cellShingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada. 355-356 [doi]
• Built-in self at-speed delay binning and calibration mechanism in wireless test platformChen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng. 357-358 [doi]
• Dynamic voltage domain assignment technique for low power performance manageable cell based designElone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo. 359-360 [doi]
• Adaptive performance control with embedded timing error predictive sensors for subthreshold circuitsHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. 361-362 [doi]
• A 60GHz direct-conversion transmitter in 65nm CMOS technologyNaoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa. 363-364 [doi]
• An electrically adjustable 3-terminal regulator with post-fabrication level-trimming functionHiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura. 365-366 [doi]
• Fine resolution double edge clipping with calibration technique for built-in at-speed delay testingChen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng. 367-368 [doi]
• Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gatingDaisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo. 369-370 [doi]
• A WiMAX turbo decoder with tailbiting BIP architectureHiroaki Arai, Naoto Miyamoto, Koji Kotani, Hisanori Fujisawa, Takashi Ito. 371-372 [doi]
• Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurementNaoto Miyamoto, Tadahiro Ohmi. 373-374 [doi]
• Design and chip implementation of an instruction scheduling free ubiquitous processorMasa-Aki Fukase, Ryosuke Murakami, Tomoaki Sato. 375-376 [doi]
• MuCCRA-3: a low power dynamically reconfigurable processor arrayYoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano. 377-378 [doi]
• Rapid prototyping on a structured ASIC fabricSteve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong, Oliver C. S. Choy. 379-380 [doi]
• A high performance low complexity joint transceiver for closed-loop MIMO applicationsJian-Lung Tzeng, Chien-Jen Huang, Yu-Han Yuan, Hsi-Pin Ma. 381-382 [doi]
• A fast symbolic computation approach to statistical analysis of mesh networks with multiple sourcesZhigang Hao, Guoyong Shi. 383-388 [doi]
• Minimizing clock latency range in robust clock tree synthesisWen-Hao Liu, Yih-Lang Li, Hui-Chi Chen. 389-394 [doi]
• Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimizationXin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang. 395-400 [doi]
• Improved clock-gating control scheme for transparent pipelineJung Hwan Choi, Byung-Guk Kim, Aurobindo Dasgupta, Kaushik Roy. 401-406 [doi]
• Scan-based attack against elliptic curve cryptosystemsRyuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 407-412 [doi]
• Secure and testable scan design using extended de Bruijn graphsHideo Fujiwara, Marie Engelene J. Obien. 413-418 [doi]
• Correlating system test Fmax with structural test Fmax and process monitoring measurementsJanine Chen, Jing Zeng, Li-C. Wang, Michael Mateja. 419-424 [doi]
• Guided gate-level ATPG for sequential circuits using a high-level test generation approachBijan Alizadeh, Masahiro Fujita. 425-430 [doi]
• Optimizing power and performance for reliable on-chip networksAditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan. 431-436 [doi]
• A low latency wormhole router for asynchronous on-chip networksWei Song, Doug Edwards. 437-443 [doi]
• Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designsTsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin. 444-449 [doi]
• Workload capacity considering NBTI degradation in multi-core systemsJin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang. 450-455 [doi]
• Design and verification methods of Toshiba's wireless LAN baseband SoCMasanori Kuwahara. 457-463 [doi]
• SOC for car navigation system with a 55.3GOPS image recognition engineHiroyuki Hamasaki, Yasuhiko Hoshi, Atsushi Nakamura, Akihiro Yamamoto, Hideaki Kido, Shoji Muramatsu. 464-465 [doi]
• A dual-MST approach for clock network synthesisJingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young. 467-473 [doi]
• Buffered clock tree sizing for skew minimization under power and thermal budgetsKrit Athikulwongse, Xin Zhao, Sung Kyu Lim. 474-479 [doi]
• Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gatingShih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan. 480-485 [doi]
• Clock tree embedding for 3D ICsTak-Yung Kim, Taewhan Kim. 486-491 [doi]
• Improved weight assignment for logic switching activity during at-speed test pattern generationMeng-Fan Wu, Hsin-Cheih Pan, T. H. Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng. 493-498 [doi]
• Graph partition based path selection for testing of small delay defectsZijian He, Tao Lv, Huawei Li, Xiaowei Li. 499-504 [doi]
• Functional and partially-functional skewed-load testsIrith Pomeranz, Sudhakar M. Reddy. 505-510 [doi]
• Emulating and diagnosing IR-drop by using dynamic SDFKe Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor. 511-516 [doi]
• Application-specific 3D Network-on-Chip design using simulated allocationPingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar. 517-522 [doi]
• A3MAP: architecture-aware analytic mapping for networks-on-chipWooyoung Jang, David Z. Pan. 523-528 [doi]
• Efficient throughput-guarantees for latency-sensitive networks-on-chipJonas Diemer, Rolf Ernst, Michael Kauschke. 529-534 [doi]
• Floorplanning and topology generation for application-specific network-on-chipBei Yu, Sheqin Dong, Song Chen, Satoshi Goto. 535-540 [doi]
• Is 3D integration an opportunity or just a hype?Jin-Fu Li, Cheng-Wen Wu. 541-543 [doi]
• An industrial perspective of 3D IC integration technology: from the viewpoint of design technologyKyu-Myung Choi. 544-545 [doi]
• Homogeneous integration for 3D IC with TSVDing-Ming Kwai. 546-547
• Configurable multi-product floorplanningQiang Ma 0002, Martin D. F. Wong, Kai-Yuan Chao. 549-554 [doi]
• UFO: unified convex optimization algorithms for fixed-outline floorplanningJai-Ming Lin, Hsi Hung. 555-560 [doi]
• Fixed-outline thermal-aware 3D floorplanningLinfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young. 561-567 [doi]
• A hierarchical bin-based legalizer for standard-cell designs with minimal disturbanceYu-Min Lee, Tsung-You Wu, Po-Yi Chiang. 568-573 [doi]
• An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variationJungsoo Kim, Younghoon Lee, Sungjoo Yoo, Chong-Min Kyung. 575-580 [doi]
• Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical designJun Seomun, Seungwhun Paik, Youngsoo Shin. 581-586 [doi]
• Dynamic power estimation for deep submicron circuits with process variationQuang Dinh, Deming Chen, Martin D. F. Wong. 587-592 [doi]
• Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processorsDongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu. 593-599 [doi]
• Managing verification error traces with bounded model debuggingSean Safarpour, Andreas G. Veneris, Farid N. Najm. 601-606 [doi]
• Automatic assertion extraction via sequential data mining of simulation tracesPo-Hsien Chang, Li-C. Wang. 607-612 [doi]
• Automatic constraint generation for guided random simulationHu-Hsi Yeh, Chung-Yang Huang. 613-618 [doi]
• A method for debugging of pipelined processors in formal verification by correspondence checkingMiroslav N. Velev, Ping Gao 0002. 619-624 [doi]
• Resilient design in scaled CMOS for energy efficiencyJames Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De. 625 [doi]
• Benefits and barriers for probabilistic designSiva Narendra. 626-627
• A probabilistic Boolean logic for energy efficient circuit and system designLakshmi N. Chakrapani, Krishna V. Palem. 628-635 [doi]
• A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithographyJae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan. 637-644 [doi]
• A robust pixel-based RET optimization algorithm independent of initial conditionsJinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, Min-Chun Tsai. 645-650 [doi]
• A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effectsKuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu. 651-656 [doi]
• Dead via minimization by simultaneous routing and redundant via insertionChih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li. 657-662 [doi]
• Statistical timing verification for transparently latched circuits through structural graph traversalXingliang Yuan, Jia Wang. 663-668 [doi]
• A unified multi-corner multi-mode static timing analysis engineJing-Jia Nian, Shihgeng Tsai, Chung-Yang (Ric) Huang. 669-674 [doi]
• Statistical time borrowing for pulsed-latch circuit designsSeungwhun Paik, Lee-eun Yu, Youngsoo Shin. 675-680 [doi]
• Design time body bias selection for parametric yield improvementCheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David Blaauw. 681-688 [doi]
• Minimizing leakage power in aging-bounded high-level synthesis with design time multi-::::V::::::::::th:::::: assignmentYibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach. 689-694 [doi]
• A global interconnect reduction technique during high level synthesisTaemin Kim, Xun Liu. 695-700 [doi]
• Incremental high-level synthesisLuciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama. 701-706 [doi]
• A high-level synthesis flow for custom instruction set extensions for application-specific processorsNagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul. 707-712 [doi]
• Computer-aided recoding for multi-core systemsRainer Dömer. 713-716 [doi]
• TLM automation for multi-core designSamar Abdi. 717-724 [doi]
• Platform modeling for exploration and synthesisAndreas Gerstlauer, Gunar Schirner. 725-731 [doi]
• Application of ESL synthesis on GSM edge algorithm for base stationAlan P. Su. 732-738 [doi]
• Analyzing electrical effects of RTA-driven local anneal temperature variationVivek Joshi, Kanak Agarwal, Dennis Sylvester, David Blaauw. 739-744 [doi]
• Physical design techniques for optimizing RTA-induced variationsYaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar. 745-750 [doi]
• On confidence in characterization and application of variation modelsLerong Cheng, Puneet Gupta, Lei He. 751-756 [doi]
• Incremental solution of power grids using random walksBaktash Boghrati, Sachin S. Sapatnekar. 757-762 [doi]
• Efficient power grid integrity analysis using on-the-fly error check and reductionDuo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai. 763-768 [doi]
• PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimizationLi Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong. 769-774 [doi]
• Gate delay estimation in STA under dynamic power supply noiseTakaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto. 775-780 [doi]
• Parametric yield driven resource binding in behavioral synthesis with multi-::::V::::::::::th::::::::::/V::::::::::dd:::::: libraryYibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach. 781-786 [doi]
• Optimizing blocks in an SoC using symbolic code-statement reachability analysisHong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo. 787-792 [doi]
• High level event driven thermal estimation for thermal aware task allocation and schedulingJin Cui, Douglas L. Maskell. 793-798 [doi]
• Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCsFabrizio Ferrandi, Christian Pilato, Donatella Sciuto, Antonino Tumeo. 799-804 [doi]
• -Possibility of ESL-: a software centric system design for multicore SoC in the upstream phaseKoichiro Yamashita. 805-808 [doi]
• Design of complex image processing systems in ESLBenjamin Carrión Schäfer, Ashish Trambadia, Kazutoshi Wakabayashi. 809-814 [doi]
• PAC duo system power estimation at ESLWen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang. 815-820 [doi]
• A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an exampleW. M. Young, Chua-Huang Huang, Alan P. Su, C. P. Jou, Fu-Lung Hsueh. 821-824 [doi]
• Slack redistribution for graceful degradation under voltage overscalingAndrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori. 825-831 [doi]
• A decoder-based switch box to mitigate soft errors in SRAM-based FPGAsHassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi. 832-837 [doi]
• On process-aware 1-D standard cell designHongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao. 838-842 [doi]
• D-A converter based variation analysis for analog layout designBo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake. 843-848 [doi]
• Rule-based optimization of reversible circuitsMona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani. 849-854 [doi]
• Variation tolerant logic mapping for crossbar array nano architecturesCihan Tunc, Mehdi Baradaran Tahoori. 855-860 [doi]
• Generalised threshold gate synthesis based on AND/OR/NOT representation of Boolean functionMarek A. Bawiec, Maciej Nikodem. 861-866 [doi]
• Novel dual-::::V::::::th:: independent-gate FinFET circuitsMasoud Rostami, Kartik Mohanram. 867-872 [doi]
• Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCsShervin Sharifi, Ayse Kivilcim Coskun, Tajana Simunic Rosing. 873-878 [doi]
• Energy efficient joint scheduling and multi-core interconnect designCathy Qun Xu, Chun Jason Xue, Yi He, Edwin Hsing-Mean Sha. 879-884 [doi]
• Dynamic and adaptive allocation of applications on MPSoC platformsAndreas Schranzhofer, Jian-Jia Chen, Luca Santinelli, Lothar Thiele. 885-890 [doi]
• Cool and save: cooling aware dynamic workload scheduling in multi-socket CPU systemsRaid Zuhair Ayoub, Tajana Simunic Rosing. 891-896 [doi]
• MPSoC programming using the MAPS compilerRainer Leupers, Jerónimo Castrillón. 897-902 [doi]
• System-level development of embedded softwareGunar Schirner, Andreas Gerstlauer, Rainer Dömer. 903-909 [doi]