Minimizing clock latency range in robust clock tree synthesis - researchr publication

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Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen. Minimizing clock latency range in robust clock tree synthesis. In Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010. pages 389-394, IEEE, 2010. [doi]

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