Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen. Minimizing clock latency range in robust clock tree synthesis. In Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010. pages 389-394, IEEE, 2010. [doi]
@inproceedings{LiuLC10-7,
title = {Minimizing clock latency range in robust clock tree synthesis},
author = {Wen-Hao Liu and Yih-Lang Li and Hui-Chi Chen},
year = {2010},
doi = {10.1109/ASPDAC.2010.5419849},
url = {http://dx.doi.org/10.1109/ASPDAC.2010.5419849},
researchr = {https://researchr.org/publication/LiuLC10-7},
cites = {0},
citedby = {0},
pages = {389-394},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010},
publisher = {IEEE},
isbn = {978-1-60558-837-7},
}