Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin. Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. In Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010. pages 444-449, IEEE, 2010. [doi]
Abstract is missing.